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AJvYcCUF0+V37RRQwe7yv65TYhnK9H0alLQkCo15hpydUGg1teg+AXnjSezMrhHq5Q4rN9kDoiNdBzrOkWuVx2T+fWwtjVfh1000ODUQqUMHHXp5s92uNlw0ibgWFVBV+ySME8VI7SeViXnGyUKLjoMjkAFOfG5sdeF6M9tslYnMGm/li2GV6A== X-Gm-Message-State: AOJu0YzwwJbKSed/0lZK7pHE0zeARqHdaZB+d/QcoNBXi9WWQIiDbyor U3b3WzUh9HgODlvge8nuVBPfu5iwhDta9s9sWqjWNFD332pssjaDWDAEochbC49aAVRUNQSuhL5 xAyXN7SstwKfnQmxRG0UlTWIGGLM= X-Received: by 2002:a05:6e02:1a09:b0:36c:51f9:716a with SMTP id s9-20020a056e021a0900b0036c51f9716amr12210835ild.13.1714978229138; Sun, 05 May 2024 23:50:29 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <1714967359-27905-1-git-send-email-shengjiu.wang@nxp.com> <1714967359-27905-2-git-send-email-shengjiu.wang@nxp.com> <05365b5a-0398-4382-9646-a1586468ed10@kernel.org> In-Reply-To: <05365b5a-0398-4382-9646-a1586468ed10@kernel.org> From: Shengjiu Wang Date: Mon, 6 May 2024 14:50:18 +0800 Message-ID: Subject: Re: [PATCH 1/4] dt-bindings: clock: imx8mp: Add #reset-cells property To: Krzysztof Kozlowski Cc: Shengjiu Wang , abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, marex@denx.de, imx@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, May 6, 2024 at 2:24=E2=80=AFPM Krzysztof Kozlowski wrote: > > On 06/05/2024 05:49, Shengjiu Wang wrote: > > Make audiomix block control a reset provider for > > Enhanced Audio Return Channel (eARC). > > Why? Commit msg should explain that. Why suddenly this became reset > coontroller? Does it represent hardware? > Yes. The Audio BLK_CTRL contains clock distribution and gating controls, as well as reset handling to several of the AUDIOMIX peripherals. The register at offset 0x200 controls the EARC PHY and Controller's reset. Best regards Shengjiu Wang > > > Best regards, > Krzysztof >