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h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=AzVWkB055SnLz5VppuwlXKdiusNLAQRaDUsZlW0hN9qA+J/nll4r5UkP8vlD14Z04 MwMz7ERbPa5/gsP09ELdQK0Zl4tI0Rz33njl7MQILs2KEGUR+rLvV/VrUWE5fqSucR 9sPzMjSV+1kYfDM8Cr5H6QXEUbco778n0GLzbQvg= Received: from [127.0.0.1] (unknown [IPv6:2001:470:683e::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384)) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id D7CAB66BDF; Mon, 6 May 2024 05:28:59 -0400 (EDT) Message-ID: <8a8135eb0f1dc724cfbb4402dc6daf08db5b0bc7.camel@xry111.site> Subject: Re: [PATCH] LoongArch: Update the flush cache policy From: Xi Ruoyao To: Li Jun , chenhuacai@kernel.org, kernel@xen0n.name, lvjianmin@loongson.cn, dongbiao@loongson.cn, zhangbaoqi@loongson.cn Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Date: Mon, 06 May 2024 17:28:58 +0800 In-Reply-To: <20240506092419.4109941-1-lijun01@kylinos.cn> References: <20240506092419.4109941-1-lijun01@kylinos.cn> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2024-05-06 at 17:24 +0800, Li Jun wrote: > fix when LoongArch s3 resume, Can't find image information >=20 > Signed-off-by: Li Jun > Signed-off-by: Baoqi Zhang > Signed-off-by: Jianmin Lv > Signed-off-by: Biao Dong > --- > =C2=A0arch/loongarch/mm/cache.c | 24 +++++++++++++++++++++++- > =C2=A01 file changed, 23 insertions(+), 1 deletion(-) >=20 > diff --git a/arch/loongarch/mm/cache.c b/arch/loongarch/mm/cache.c > index 6be04d36ca07..52872fa0e5d8 100644 > --- a/arch/loongarch/mm/cache.c > +++ b/arch/loongarch/mm/cache.c > @@ -63,6 +63,28 @@ static void flush_cache_leaf(unsigned int leaf) > =C2=A0 } while (--nr_nodes > 0); > =C2=A0} > =C2=A0 > +static void flush_cache_last_level(unsigned int leaf) > +{ > + u64 addr; > + int i, j, nr_nodes, way_size; > + struct cache_desc *cdesc =3D current_cpu_data.cache_leaves + > leaf; > + > + nr_nodes =3D loongson_sysconf.nr_nodes; > + > + addr =3D CSR_DMW1_BASE; > + iocsr_write32(0x1, 0x280); > + way_size =3D cdesc->sets * cdesc->linesz; > + do { > + for (i =3D 0; i < (cdesc->ways * 3); i++) { > + for (j =3D 0; j < (cdesc->sets); j++) { > + *(volatile u32 *)addr; ??? what does this line do? --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University