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Date: Mon, 6 May 2024 18:41:08 +0200
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Richard Weinberger <richard@nod.at>, Vignesh Raghavendra
 <vigneshr@ti.com>, linux-mtd@lists.infradead.org,
 linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/4] mtd: nand: mxc_nand: disable subpage reads
Message-ID: <20240506184108.7b1b344d@xps-13>
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Hi Sascha,

s.hauer@pengutronix.de wrote on Mon, 22 Apr 2024 12:53:38 +0200:

> On Fri, Apr 19, 2024 at 11:46:57AM +0200, Miquel Raynal wrote:
> > Hi Sascha,
> >=20
> > s.hauer@pengutronix.de wrote on Thu, 18 Apr 2024 13:43:15 +0200:
> >  =20
> > > On Thu, Apr 18, 2024 at 11:32:44AM +0200, Miquel Raynal wrote: =20
> > > > Hi Sascha,
> > > >=20
> > > > s.hauer@pengutronix.de wrote on Thu, 18 Apr 2024 08:48:08 +0200:
> > > >    =20
> > > > > On Wed, Apr 17, 2024 at 09:13:31AM +0200, Sascha Hauer wrote:   =
=20
> > > > > > The NAND core enabled subpage reads when a largepage NAND is us=
ed with
> > > > > > SOFT_ECC. The i.MX NAND controller doesn't support subpage read=
s, so
> > > > > > clear the flag again.
> > > > > >=20
> > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > > > ---
> > > > > >  drivers/mtd/nand/raw/mxc_nand.c | 2 ++
> > > > > >  1 file changed, 2 insertions(+)
> > > > > >=20
> > > > > > diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand=
/raw/mxc_nand.c
> > > > > > index f44c130dca18d..19b46210bd194 100644
> > > > > > --- a/drivers/mtd/nand/raw/mxc_nand.c
> > > > > > +++ b/drivers/mtd/nand/raw/mxc_nand.c
> > > > > > @@ -1667,6 +1667,8 @@ static int mxcnd_probe(struct platform_de=
vice *pdev)
> > > > > >  	if (err)
> > > > > >  		goto escan;
> > > > > > =20
> > > > > > +	this->options &=3D ~NAND_SUBPAGE_READ;
> > > > > > +     =20
> > > > >=20
> > > > > Nah, it doesn't work like this. It turns out the BBT is read using
> > > > > subpage reads before we can disable them here.
> > > > >
> > > > > This is the code in nand_scan_tail() we stumble upon:
> > > > >=20
> > > > > 	/* Large page NAND with SOFT_ECC should support subpage reads */
> > > > > 	switch (ecc->engine_type) {
> > > > > 	case NAND_ECC_ENGINE_TYPE_SOFT:
> > > > > 		if (chip->page_shift > 9)
> > > > > 			chip->options |=3D NAND_SUBPAGE_READ;
> > > > > 		break;
> > > > >=20
> > > > > 	default:
> > > > > 		break;
> > > > > 	}
> > > > >=20
> > > > > So the code assumes subpage reads are ok when SOFT_ECC is in use,=
 which
> > > > > in my case is not true. I guess some drivers depend on the
> > > > > NAND_SUBPAGE_READ bit magically be set, so simply removing this c=
ode is
> > > > > likely not an option.  Any ideas what to do?   =20
> > > >=20
> > > > Can you elaborate why subpage reads are not an option in your
> > > > situation? While subpage writes depend on chip capabilities, reads
> > > > however should always work: it's just the controller selecting the
> > > > column where to start and then reading less data than it could from=
 the
> > > > NAND cache. It's a very basic NAND controller feature, and I rememb=
er
> > > > this was working on eg. an i.MX27.   =20
> > >=20
> > > On the i.MX27 reading a full 2k page means triggering one read operat=
ion
> > > per 512 bytes in the NAND controller, so it would be possible to read
> > > subpages by triggering only one read operation instead of four in a r=
ow.
> > >=20
> > > The newer SoCs like i.MX25 always read a full page with a single read
> > > operation. We could likely read subpages by temporarily configuring t=
he
> > > controller for a 512b page size NAND.
> > >=20
> > > I just realized the real problem comes with reading the OOB data. With
> > > software BCH the NAND layer hardcodes the read_subpage hook to
> > > nand_read_subpage() which uses nand_change_read_column_op() to read t=
he
> > > OOB data. This uses NAND_CMD_RNDOUT and I have now idea if/how this c=
an
> > > be implemented in the i.MX NAND driver. Right now the controller inde=
ed
> > > reads some data and then the SRAM buffer really contains part of the
> > > desired OOB data, but also part of the user data. =20
> >=20
> > NAND_CMD_RNDOUT is impossible to avoid, =20
>=20
> Apparently it has been possible until now. NAND_CMD_RNDOUT has never
> been used with this driver and it also doesn't work like expected.
>=20
> One problem is that the read_page_raw() and write_page_raw() are not
> implemented like supposed by the NAND layer. The i.MX NAND controller
> uses a syndrome type ECC layout, meaning that the user data and OOB data
> is interleaved, so the raw r/w functions should normally pass/expect the
> page data in interleaved format. Unfortunately the raw functions are not
> implemented like that, instead they detangle the data themselves. This
> also means that setting the cursor using NAND_CMD_RNDOUT will not put
> the cursor at a meaningful place, as the raw functions are not really
> exect/return the raw page data.
>=20
> This could be fixed, but the raw operations are also exposed to
> userspace, so fixing these would mean that we might break some userspace
> applications.

As answered to patch 3/4 I believe you need other raw page helpers for
the software ECC path, just because the existing functions are tight to
the on-host ECC logic and do what they are expected to do (I believe).

Creating another set of raw page helpers should be straightforward to
do if that's really needed (mainly for performance purposes, but we're
not yet there). Using the core helpers should work, the only thing is
supporting properly the NAND_CMD_RNDOUT path, which should be possible
at a rather low cost, it really is a very very basic command, I know no
controller without this feature, even old ones.

> The other point is that with using software BCH ecc the NAND layer
> requests me to read 7 bytes at offset 0x824. This can't be really
> implemented in the i.MX NAND driver. It only allows us to read a full
> 512 byte subpage, so whenever the NAND layer requests me to read a few
> bytes the controller will always transfer 512 bytes from which I then
> ignore most of it (and possibly trigger another 512 bytes transfer when
> reading the ECC for the next subpage).

If you manage to get the NAND_CMD_RNDOUT op working I believe you'll be
tempted to use memcpy32_fromio() with just a slightly rounded up length.

> I think these issues can all be handled somehow, but this comes at a
> rather high price, both in effort and the risk of breaking userspace.
> It would be far easier to tell the NAND layer not to do subpage reads.

I understand it may feel like that but that is likely not the right
approach. I just think about another possibility: using monolithic
reads if the controller is too constrained this way you might end up
avoiding the RNDOUT command (might require a bit of tweaking in the
core, I no longer remember exactly).

Good luck, I really appreciate this effort.
Miqu=C3=A8l