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From: Krishna Yarlagadda <kyarlagadda@nvidia.com>
To: <linux-tegra@vger.kernel.org>, <devicetree@vger.kernel.org>,
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Subject: [RFC PATCH 11/11] arm64: tegra: SDHCI timing settings
Date: Tue, 7 May 2024 04:21:39 +0530
Message-ID: <20240506225139.57647-12-kyarlagadda@nvidia.com>
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Set SDHCI timing registers through config settings for
Tegra234 chip and P3701 board.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi | 32 ++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
index 832538e45797..f9a92853b04a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
@@ -442,5 +442,37 @@ standard {
 			};
 		};
 
+		mmc@3400000 {
+			config {
+
+				mmc-hs200 {
+					nvidia,num-tuning-iter = <0x2>;
+				};
+
+				uhs-sdr104 {
+					nvidia,num-tuning-iter = <0x2>;
+				};
+
+				uhs-sdr50 {
+					nvidia,num-tuning-iter = <0x4>;
+				};
+
+			};
+		};
+
+		mmc@3460000 {
+			config {
+
+				mmc-hs200 {
+					nvidia,num-tuning-iter = <0x2>;
+				};
+
+				mmc-hs400 {
+					nvidia,num-tuning-iter = <0x2>;
+				};
+
+			};
+		};
+
 	};
 };
-- 
2.43.2