Received-SPF: pass (google.com: domain of linux-kernel+bounces-170700-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161;
Content-Type: text/plain;
	charset=utf-8
Precedence: bulk
Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3774.500.171.1.1\))
Subject: Re: [PATCH 4/8] riscv: Add PLATFORM_MAY_SUPPORT_RISCV_ISA_SVPBMT
 Kconfig option
From: Jessica Clarke <jrtc27@jrtc27.com>
In-Reply-To: <20240506-compile_kernel_with_extensions-v1-4-5c25c134c097@rivosinc.com>
Date: Tue, 7 May 2024 06:40:52 +0100
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
 Palmer Dabbelt <palmer@dabbelt.com>,
 Albert Ou <aou@eecs.berkeley.edu>,
 Conor Dooley <conor.dooley@microchip.com>,
 Song Liu <song@kernel.org>,
 Xi Wang <xi.wang@gmail.com>,
 =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>,
 =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>,
 linux-riscv <linux-riscv@lists.infradead.org>,
 LKML <linux-kernel@vger.kernel.org>
Content-Transfer-Encoding: quoted-printable
Message-Id: <11F5B269-05DD-448E-9F85-878E84A5654F@jrtc27.com>
References: <20240506-compile_kernel_with_extensions-v1-0-5c25c134c097@rivosinc.com>
 <20240506-compile_kernel_with_extensions-v1-4-5c25c134c097@rivosinc.com>
To: Charlie Jenkins <charlie@rivosinc.com>

On 7 May 2024, at 02:40, Charlie Jenkins <charlie@rivosinc.com> wrote:
>=20
> Svpbmt would not benefit from having =
PLATFORM_SUPPORTS_RISCV_ISA_SVPBMT
> so just rename RISCV_ISA_SVPBMT to =
PLATFORM_MAY_SUPPORT_RISCV_ISA_SVPBMT
> and move the definition to Kconfig.isa.
>=20
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
> arch/riscv/Kconfig     | 17 -----------------
> arch/riscv/Kconfig.isa | 17 +++++++++++++++++
> 2 files changed, 17 insertions(+), 17 deletions(-)
>=20
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 9c3a4347953b..22303a3ab59e 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -484,23 +484,6 @@ config RISCV_ALTERNATIVE_EARLY
> help
>  Allows early patching of the kernel for special errata
>=20
> -config RISCV_ISA_SVPBMT
> - bool "Svpbmt extension support for supervisor mode page-based memory =
types"
> - depends on 64BIT && MMU
> - depends on RISCV_ALTERNATIVE
> - default y
> - help
> -   Add support for the Svpbmt ISA-extension (Supervisor-mode:
> -   page-based memory types) in the kernel when it is detected at =
boot.
> -
> -   The memory type for a page contains a combination of attributes
> -   that indicate the cacheability, idempotency, and ordering
> -   properties for access to that page.
> -
> -   The Svpbmt extension is only available on 64-bit cpus.
> -
> -   If you don't know what to do here, say Y.
> -
> config TOOLCHAIN_HAS_ZBB
> bool
> default y
> diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa
> index 37585bcd763e..50e217dc5719 100644
> --- a/arch/riscv/Kconfig.isa
> +++ b/arch/riscv/Kconfig.isa
> @@ -168,3 +168,20 @@ config PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT
>  not support Svnapot.
>=20
> endchoice
> +
> +config RISCV_ISA_SVPBMT

Hi Charlie,
Despite the subject and body you haven=E2=80=99t renamed it in this =
patch?

Jess

> + bool "Svpbmt extension support for supervisor mode page-based memory =
types"
> + depends on 64BIT && MMU
> + depends on RISCV_ALTERNATIVE
> + default y
> + help
> +   Add support for the Svpbmt ISA-extension (Supervisor-mode:
> +   page-based memory types) in the kernel when it is detected at =
boot.
> +
> +   The memory type for a page contains a combination of attributes
> +   that indicate the cacheability, idempotency, and ordering
> +   properties for access to that page.
> +
> +   The Svpbmt extension is only available on 64-bit cpus.
> +
> +   If you don't know what to do here, say Y.
>=20
> --=20
> 2.44.0
>=20
>=20
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv