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[142.68.80.239]) by smtp.gmail.com with ESMTPSA id v16-20020a056808005000b003c96907bd58sm981178oic.50.2024.05.07.07.54.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 May 2024 07:54:57 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1s4MDY-00825J-2j; Tue, 07 May 2024 11:54:56 -0300 Date: Tue, 7 May 2024 11:54:56 -0300 From: Jason Gunthorpe To: Zong Li Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, tjeznach@rivosinc.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, kevin.tian@intel.com, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org Subject: Re: [PATCH RFC RESEND 4/6] iommu/riscv: support nested iommu for getting iommu hardware information Message-ID: <20240507145456.GH901876@ziepe.ca> References: <20240507142600.23844-1-zong.li@sifive.com> <20240507142600.23844-5-zong.li@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240507142600.23844-5-zong.li@sifive.com> On Tue, May 07, 2024 at 10:25:58PM +0800, Zong Li wrote: > +{ > + struct riscv_iommu_device *iommu = dev_to_iommu(dev); > + struct iommu_hw_info_riscv_iommu *info; > + > + if (!iommu) > + return ERR_PTR(-ENODEV); This is not possible, don't include impossible checks like this. > + info = kzalloc(sizeof(*info), GFP_KERNEL); > + if (!info) > + return ERR_PTR(-ENOMEM); > + > + info->capability = iommu->caps; > + info->fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL); > + > + *length = sizeof(*info); > + *type = IOMMU_HW_INFO_TYPE_RISCV_IOMMU; > + > + return info; > +} > + > static int riscv_iommu_device_domain_type(struct device *dev) > { > return 0; > @@ -1560,6 +1582,7 @@ static void riscv_iommu_release_device(struct device *dev) > static const struct iommu_ops riscv_iommu_ops = { > .pgsize_bitmap = SZ_4K, > .of_xlate = riscv_iommu_of_xlate, > + .hw_info = riscv_iommu_hw_info, > .identity_domain = &riscv_iommu_identity_domain, > .blocked_domain = &riscv_iommu_blocking_domain, > .release_domain = &riscv_iommu_blocking_domain, > diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h > index 1dfeaa2e649e..ec9aafd7d373 100644 > --- a/include/uapi/linux/iommufd.h > +++ b/include/uapi/linux/iommufd.h > @@ -475,15 +475,28 @@ struct iommu_hw_info_vtd { > __aligned_u64 ecap_reg; > }; > > +/** > + * struct iommu_hw_info_riscv_iommu - RISCV IOMMU hardware information > + * > + * @capability: Value of RISC-V IOMMU capability register > + * @fctl: Value of RISC-V IOMMU feature control register > + */ Please call out explictly what spec these values come from. > +struct iommu_hw_info_riscv_iommu { > + __aligned_u64 capability; > + __u32 fctl; > +}; Add explicit padding here Jason