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Message-ID: <a4347e43-06f7-4ede-b50f-554d1194a1f6@linux.dev>
Date: Tue, 7 May 2024 16:07:18 -0400
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Subject: Re: [PATCH v2 1/7] dt-bindings: pci: xilinx-nwl: Add phys
To: Rob Herring <robh@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>,
 =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
 linux-pci@vger.kernel.org, Michal Simek <michal.simek@amd.com>,
 Bjorn Helgaas <bhelgaas@google.com>,
 Thippeswamy Havalige <thippeswamy.havalige@amd.com>,
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 Conor Dooley <conor+dt@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 devicetree@vger.kernel.org
References: <20240506161510.2841755-1-sean.anderson@linux.dev>
 <20240506161510.2841755-2-sean.anderson@linux.dev>
 <20240507200640.GA955773-robh@kernel.org>
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From: Sean Anderson <sean.anderson@linux.dev>
In-Reply-To: <20240507200640.GA955773-robh@kernel.org>
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On 5/7/24 16:06, Rob Herring wrote:
> On Mon, May 06, 2024 at 12:15:04PM -0400, Sean Anderson wrote:
>> Add phys properties so Linux can power-on/configure the GTR
>> transcievers.
>> 
>> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
>> ---
>> 
>> Changes in v2:
>> - Remove phy-names
>> - Add an example
>> 
>>  Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 6 ++++++
>>  1 file changed, 6 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> index 426f90a47f35..693b29039a9b 100644
>> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> @@ -61,6 +61,10 @@ properties:
>>    interrupt-map:
>>      maxItems: 4
>>  
>> +  phys:
>> +    minItems: 1
>> +    maxItems: 4
> 
> I assume this is 1 phy per lane, but don't make me assume and define it.
> 
> Rob

It's one per lane. I'll add that to the description.

--Sean