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Tue, 7 May 2024 22:57:01 -0700 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v7 3/6] iommu/arm-smmu-v3: Enforce arm_smmu_cmdq_build_sync_cmd Date: Tue, 7 May 2024 22:56:51 -0700 Message-ID: <52845c9fdfdd7f38a694e7727f3eabbd10e9f8ee.1715147377.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CA:EE_|SJ2PR12MB8847:EE_ X-MS-Office365-Filtering-Correlation-Id: a42c33d5-bb45-47bb-67d1-08dc6f23b319 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|376005|1800799015|82310400017; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?TOyMw3N7k5IxgQwuPTsIkeKVvN7U3kg1wRSD2LK/v1Y/BPzNPmwJWp/V1SCY?= =?us-ascii?Q?FU6u3S1OQJyyN84WFxYx54RhP39XxfHwkwfVfaymaMJnsUaIT9FUFyIH2L3W?= =?us-ascii?Q?FvQqRB2D2i2azkggcG16qcgyV0VM/QrlfI5ZAGLXUMmqZMDDfcMSRrUEikmX?= =?us-ascii?Q?kYROH3TPDkghfqkEu8dbvbwPfkt6oiOu3VszwXITe0CmpniaaDj4IvnIXcbs?= =?us-ascii?Q?M5IVi3Suo1t9KrAeu+wvxsINZbQVGWoSSaEBy4IPDySCKxjrqzOfBW7J1EHn?= =?us-ascii?Q?ZFIwnIOrQxGl/qu4GZj2a30qtU80TjFS0oF2WNkQnqVvMeEZXG+HttHPUOcu?= =?us-ascii?Q?lrhGNMV+XVRlPS5SeMppBRVSrrzrUyKeEhdJjDsdt8Gh9Fdc2yoTT512gWuB?= =?us-ascii?Q?zbZU7tvK5uZ7Rfs1PuCefkWQVtsf9g3/zysXtnjlfiDTkdAxv4/1D73IdMF/?= =?us-ascii?Q?SCM1/2DEDOLon1okjHyw2iKGRJ1AFWh60p9Y9d2ZPEmuRMY6qTI+o8kMe1Yo?= =?us-ascii?Q?+qmsNbZ4iyN6v84V8PgFoJweXqErqRnkVddBDjWZN4D+Fa+vdLnu/aB10Fyl?= =?us-ascii?Q?rkoLTpkbUOP4y69Bg7rIAnWT7IML2JywlyT7huzSZbLB5na7qerjC1NYLiid?= =?us-ascii?Q?inVOkOfIpSmMNWwv2q8GVECdUHGEnGygRmfT6NBAOitjdQdIkLmwQefuP50J?= =?us-ascii?Q?k4GbL5vg2MphYY7ZLB18D3xgLsHyKOvpCRfmLpoKPnfEGV4kzNRWhPHFBuX2?= =?us-ascii?Q?TeDojImXZ3lWDk7z/WP0GOZdn6gKFJInI/XBVLJPJieSSpcpopjse+Mi6pDk?= =?us-ascii?Q?CZcHugkGh8KofNe4xc4Yn8LZSWBbY3Wjk1LPcMXK8uX23bmwasKPTDjUpZki?= =?us-ascii?Q?7haOAwIfra0S3XUr1HQ6lwdSVYhvl6WH8H0ulUFl7TcexmGXn84cp5P+izLt?= =?us-ascii?Q?8K3Zaey5QSZNH44pee1BPIzXX6LCnY148hTk2Xte1UG0kMRKQzvxGldxlK2r?= =?us-ascii?Q?U0WZzf31tuGj3R3VPeXCMriBcY1tKJ0u5rmbRIYKrDPclcTaEvhNrVuHupkH?= =?us-ascii?Q?V67VgbzD1ynUh/MZYTmog4hvp9mspkIMo0jqY1cMNdPSZ9NQ1meZygOBGdjL?= =?us-ascii?Q?23r/XWIc0+Y1lIZkH6RF6XXwG2rEZEnX9zetV4UUqEA5shuVwI429FjN0G8F?= =?us-ascii?Q?np0K3ijQVZaNH4CYNirdYHiBzrZYJVoE/Fjss+McZDYGspB7+bmjisj8QSJn?= =?us-ascii?Q?FtrzlIGxMaqqBkv9TBcSc9Hn+xlcV7Y6nFwa+U2QLpTjnMhHSDA/OaX2CFp0?= =?us-ascii?Q?yyXFVwJse+dxNpWuTKerBDyIcTLqRrrBGKINpDdIDYrkUPycIXXE0RNvz7W5?= =?us-ascii?Q?hFH7VymBivry5pNzZOJt5JxOkM/D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(376005)(1800799015)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 May 2024 05:57:09.8780 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a42c33d5-bb45-47bb-67d1-08dc6f23b319 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8847 There is an existing arm_smmu_cmdq_build_sync_cmd() so the driver should call it at all places other than going through arm_smmu_cmdq_build_cmd() separately. This helps the following patch that adds a CS_NONE quirk for tegra241-cmdqv driver. Note that this changes the type of CMD_SYNC in __arm_smmu_cmdq_skip_err, for ARM_SMMU_OPT_MSIPOLL=true cases, from previously a non-MSI one to an MSI one that is proven to still work by a hacking test: nvme: Adding to iommu group 10 nvme: --------hacking----------- arm-smmu-v3: unexpected global error reported (0x00000001), this could be serious arm-smmu-v3: CMDQ error (cons 0x01000022): Illegal command arm-smmu-v3: skipping command in error state: arm-smmu-v3: 0x0000000000000000 arm-smmu-v3: 0x0000000000000000 nvme: -------recovered---------- nvme nvme0: 72/0/0 default/read/poll queues nvme0n1: p1 p2 Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 -- 2 files changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 3d2962f6dbda..569bca1a8a1f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -325,16 +325,6 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); break; - case CMDQ_OP_CMD_SYNC: - if (ent->sync.msiaddr) { - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); - cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; - } else { - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); - } - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); - break; default: return -ENOENT; } @@ -350,20 +340,23 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, struct arm_smmu_queue *q, u32 prod) { - struct arm_smmu_cmdq_ent ent = { - .opcode = CMDQ_OP_CMD_SYNC, - }; + memset(cmd, 0, 1 << CMDQ_ENT_SZ_SHIFT); + cmd[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | + FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); + return; + } /* * Beware that Hi16xx adds an extra 32 bits of goodness to its MSI * payload, so the write will zero the entire command on that platform. */ - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { - ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * - q->ent_dwords * 8; - } - - arm_smmu_cmdq_build_cmd(cmd, &ent); + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); + cmd[1] = (q->base_dma + Q_IDX(&q->llq, prod) * q->ent_dwords * 8) & + CMDQ_SYNC_1_MSIADDR_MASK; } void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, @@ -380,9 +373,6 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, u64 cmd[CMDQ_ENT_DWORDS]; u32 cons = readl_relaxed(q->cons_reg); u32 idx = FIELD_GET(CMDQ_CONS_ERR, cons); - struct arm_smmu_cmdq_ent cmd_sync = { - .opcode = CMDQ_OP_CMD_SYNC, - }; dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown"); @@ -416,7 +406,7 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 8e4fbf4f50f3..180c0b1e0658 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -512,9 +512,6 @@ struct arm_smmu_cmdq_ent { } resume; #define CMDQ_OP_CMD_SYNC 0x46 - struct { - u64 msiaddr; - } sync; }; }; -- 2.43.0