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Tue, 7 May 2024 22:57:02 -0700 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v7 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV Date: Tue, 7 May 2024 22:56:52 -0700 Message-ID: <4d16c08b9d4244e1ff3836a586641ea6deb0c9cb.1715147377.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CD:EE_|CH3PR12MB9193:EE_ X-MS-Office365-Filtering-Correlation-Id: 9a102a63-044f-4b28-a791-08dc6f23b38a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|82310400017|376005|1800799015; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?B+CGURHaGWjm9KUEHvsn7bxG6FD15On0z5uelwqXbOgkj+kNvx7AE6Rqa43h?= =?us-ascii?Q?wdEl0EyJpSRuoTctXqBiA4gbT1zNoSzuSo9qwZ1KjubGeigOo4JENsSB/c0E?= =?us-ascii?Q?W2/9eI/xQGAwgS716Z/RzWbGLIXOMsLydDgu2M3urpf7AdA6GN/qrfCktqpx?= =?us-ascii?Q?JyHbWB01j6YfQMf6j5r83ABhWWlhcUukie94wXYVM+A72URLbRALBRFjp5Ak?= =?us-ascii?Q?A/OQACaAk53LsMvPHsLxEDvtZTU2n88oJgIJgcW88LHzmFmmTC1urb3RLYXb?= =?us-ascii?Q?r9x1kZHCgALFLcPTtG0DYI9663cVfcat/lYVTD9Dibz0+PjrPw9QnUBmE90c?= =?us-ascii?Q?Rha3X4+EV6HEk4TH9yd6M/UwXJq4eaaZIIeUDjnU1c3KC6Dya2NSJoVaw3K7?= =?us-ascii?Q?ptOiFCmZCh1SDkV18YJdsqgWzls5XdrIhimvH3QQE6vHez4U9L39OPtPTqzE?= =?us-ascii?Q?Y71qZD5D2NptETjzi1hRoeSdLt52M1im7j3sfxc8V7ZxYCVRxYX5KuiUAMDT?= =?us-ascii?Q?nj0kKjsjz8o0WWLfDay4V8nmqjuW//RcvQ76U9GxNa7XsFHeXO+ex3rbNjKM?= =?us-ascii?Q?NB4At4fopKAA5AIYLDdWBZJWv1x0h6sSyCcLQoPOUhwmRoA/LHVZdQtHz3+v?= =?us-ascii?Q?Cdqq53MzZpsmaN55mJe/F39DjiBih09smaoNCpAxSMh99s3U0V6F4fm7Jtys?= =?us-ascii?Q?9Tw2Oi2jxNfyfjf/+Q2hFgoDUjuNj8E3hG947NY00HegUP9fGJrhD1ox2Mju?= =?us-ascii?Q?Eodo6W8jba+Fx8KInMqfAxDAyl2Uqt4LiEoWwasjYGHEMli7S8tXlIabkxXu?= =?us-ascii?Q?nosRR+vX5/W7+JDG34D8XXgaCwiq48LG1foUo/FaKXlTcFj4kEd51QViodGC?= =?us-ascii?Q?1JJf7032jgsU1EFoFgkhqyUezGharSbcJfiigtQQbotCe6F98/yZZEzyf1gQ?= =?us-ascii?Q?/8URq3DkTvWaXi94obdrlMLspWtr/pQBorcJnfOpcX6XOdyAUJn/XDYvGeVl?= =?us-ascii?Q?kXlE8wdn+Lkh1c6sG7GzgyuW3rI+Jjghtl0xaD/VSsERxlqlITUVrY0RHbf4?= =?us-ascii?Q?lla7lFChmb9AxLnSZphhBo0OsG2052r5Ja+/6FD6SIhj4jvkHrgavW0WOU2X?= =?us-ascii?Q?DeVP92sjChXxcBgea2+zO7PcmGdnHYGyvlTrs9ju+ylcGRLjpPKYT1IGsYm6?= =?us-ascii?Q?Oeejj+19qKSaIsoRxh0/ZuwMGU9w8uaGwQmRrV8JjMXjVUgmw6zhsNKe48f0?= =?us-ascii?Q?o3pilqC3Twhv3THosGg8zlTELPFLwm9QCqRPbqV/L/JxUdz/whSydvFNx1yz?= =?us-ascii?Q?4xCOh67bxxbtAL8eLxWoLfu90hju9BbQ5o4Jsn2khiaMygjQHx2PxhYFlzCg?= =?us-ascii?Q?XrWn1jG6PSzkIoe2mY1deVRni6sR?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(82310400017)(376005)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 May 2024 05:57:10.6202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a102a63-044f-4b28-a791-08dc6f23b38a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9193 The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC. Add a quirk flag to accommodate that. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 +++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 569bca1a8a1f..2d8eb7c08a85 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -345,6 +345,11 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); + return; + } + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); return; @@ -690,7 +695,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && + !(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)) return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 180c0b1e0658..01227c0de290 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -543,6 +543,9 @@ struct arm_smmu_queue { u32 __iomem *prod_reg; u32 __iomem *cons_reg; + +#define CMDQ_QUIRK_SYNC_CS_NONE_ONLY BIT(0) /* CMD_SYNC CS field supports CS_NONE only */ + u32 quirks; }; struct arm_smmu_queue_poll { -- 2.43.0