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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?a0dwOS9HT1g4UHRUVkpQVVhNM1FhT0Z0T1VYLytlUGx5R2FqcmR0azl4Ti9y?= =?utf-8?B?S25pTmJJQVhiNlVZQUc5OUNGRndCRm5ZWnJxMzJpNlRwdCsyMXMvNk9uU0N4?= =?utf-8?B?SkFsYTZWNzJnYkdBSDU3NlU3dWEwQ0tYT3MxZmpxY2QyMTBWaC9Xc1h6ZktQ?= =?utf-8?B?Y3pqR01MbGJLOTNvKy9laVdEK29GQTRCS1B5Z3FsRlErc1E1V1R6WHN2b3lQ?= =?utf-8?B?LzVwMVJMRGgzWDQxVUVlSFRNZkRFMUdiZHhEdE1BTm1xNnFpS0ttS3REaXNl?= =?utf-8?B?TFJnT0dValZMcHEvQ213eU5xaXI2dWdiNUVaY1lCNjhJRU1nSVozTTRxN21H?= =?utf-8?B?OTk0T2cvTkNwUC85VmNyTm1tSHQzYjJSZUErL016SGNRMXI0UkQxNCsvZjIv?= =?utf-8?B?MmJ5c1ZXQjVERXFIY2lvUmVIc21zaGk0aU1adWVyMHZMWlJmNmdueHlBNjJp?= =?utf-8?B?c0VMNGVwRnNkOFA5WGJyMWR5VWtFM3ZFWU1iV1hPTkdPNU53V3pubWdnb2lI?= =?utf-8?B?cU10NlU0Z3lqdWF0MDJvMFhPNWFqS0hEY0FyYkVQbXUxcVV0YkVXdGxmSFNR?= =?utf-8?B?Tjh3MjFZb1NpT29OSlZnMWUwMUZvVW90ZnVHQ0djSk5TMGhpeERYellYdS8y?= =?utf-8?B?RFRkcG8zelJ6NEpRaWtRRkQ4cWVwc2RYcGxtOGpNTmQvNFJxRXpkMzdxaW5F?= =?utf-8?B?MUV1amVsOG0wekZ6SFMxdWdFYVRMaFlJMDdETVhxeVRoRDdPemhyRmxNYkwy?= =?utf-8?B?YnlERGYwQ2xaclovN1M3T2lnMVZ6M09YdGI3NXQwWkxMK2FCTE1waXY1aDlE?= =?utf-8?B?R3doblZPVjBPTkdCZXIwVWp3Rm5LYmpKVmhOWmNJK1h2d3pCeG84bzZVNWlX?= =?utf-8?B?RTRnTnJOSm82cTNIRFVEMUxRTWdVc2hJTlJOZklQWFRxY2MreTBINkUrSFZX?= =?utf-8?B?aW5PemRmdldaMVNLcGtwOGgrSy9OTFhTdGdNQ1RwUFJkNklhUnN6ck5iSnhp?= =?utf-8?B?V3AyN2cycEtPY1J5V0xmNlBodTZJZERKS2FKOFNaQksyVyswRTM3STlDT0lM?= =?utf-8?B?S2lTKy83cW5YaG1rUmxOS2g5ZGE2dy8xd2RIejkzbUlUbC9ZZlZ4aDZtUDh0?= =?utf-8?B?alBPV2lvUGw3anFiL0RtWnNjL3ZEdDc3VEE3N1p5K3g1dUIzMy8rZ1ZlUnV3?= =?utf-8?B?SU5BWUFWTDNtdmlUS2hCSUlLSWtzUXhDOEdNaHhJK09INzVCYzE1Q1gwNVpM?= =?utf-8?B?bkh1NW9aY3loZ1cyb1JjTGpLcDQ3WGdjUmRnWW5kcXZOdjRpV3ZkZVZtcGNs?= =?utf-8?B?aGpSZzFycmRDOU1lQWJqSlNpazZ0L0VVbVZuOTk0YVlzNGhUT0lmZjU4T1Bm?= =?utf-8?B?dlUrWG9DZ1o0OUxscjZHSHFqdVVzV2dwcGZod1VYTy9oNExnOHkzT09WWGE4?= =?utf-8?B?YWpvVXZSa3h0L3daanJjT3pCTy9vWUxZUDFJa3I0a0d2NXgzUVZ2RjZvVUVP?= =?utf-8?B?a0lMc0ZrZTR5aTdYbjJ5NDd3bVN4bXlQYmdFZzJweXloaWsxdS9zTGIwYXdx?= =?utf-8?B?Rnd5WUNUaUgzL2JsR0d1SFpxTGZ3MDB0dFBRUXc4MGFwaVJpanZwODhrUjlX?= =?utf-8?B?MVh0ZHdYVy9iSHlCdm9JT0tYTTVOeTNGcGpLL2ViMDE4YjVBc2RlcWc0clMw?= =?utf-8?B?TlhLdUYrcDh3RG9PWElLM29nemtQeGJYemFTeVJ4OGlLRS9FZXl3N0lEV1Qz?= =?utf-8?B?ZExvS2pKd00xK2pObnNwcVloYTFYbEZVMExyV1VvMVBjQTlEUExnZXlxdm5D?= =?utf-8?B?bzZUREltcUJnMXF6RDRnTUV1dDYyK1JiK3l2bjVsSGNGbDZnMjBnYU9UMGRH?= =?utf-8?B?dkN1dEh6R2hrY1VKcHBRT29yQWE2MTZ0dUEwMEFzMGcySEJTeS9ONS93cnpy?= =?utf-8?B?elA0dER3MEtWUUw5NEhLbFQ4UGdlall6bUF6TlJkUnhlT0hTTzM1emN6dVVC?= =?utf-8?B?QkI2ODBoMkxHRDVwd05lVUFFWkhERm5lWndFNkVyNFRTNlpUWlF2cHdweEJy?= =?utf-8?B?bDh6ZG9OajdNZmZOUmhiRjZ0dk5CanBYWU9qZGNIOEtBbWE2OUJFazRKNWZP?= =?utf-8?B?S05CWnFSUzgrejZzMi9VZTJFY2ozQUwzNWhuNEdXdm9sYmRqM2tpUi85aEk2?= =?utf-8?B?TWc9PQ==?= X-MS-Exchange-CrossTenant-Network-Message-Id: 779171b1-e20b-4cf4-d903-08dc6f2c86e2 X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB4965.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 May 2024 07:00:21.9545 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5TA9OO5Ij9nSx94v1eSGZwKxwVy/EdCucoU4GGTu45lBVDk0o0thIFO8TzURyfvHunv73AF9kDiQig/eBXUgcw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR11MB6152 X-OriginatorOrg: intel.com On 5/8/2024 1:27 AM, Sean Christopherson wrote: > On Mon, May 06, 2024, Weijiang Yang wrote: >> On 5/2/2024 6:40 AM, Sean Christopherson wrote: >>> On Sun, Feb 18, 2024, Yang Weijiang wrote: [...] >> For the latter, IIUC KVM still needs to expose the index within the synthetic >> namespace so that userspace can read/write the intended MSRs, of course not >> expose the synthetic MSR index via existing uAPI,  But you said the "index" >> exposed to userspace can simply  be '0' in this case, then how to distinguish >> the synthetic MSRs in userspace and KVM? And how userspace can be aware of >> the synthetic MSR index allocation in KVM? > The idea is to have a synthetic index that is exposed to userspace, and a separate > KVM-internal index for emulating accesses. The value that is exposed to userspace > can start at 0 and be a simple incrementing value as we add synthetic MSRs, as the > .type == SYNTHETIC makes it impossible for the value to collide with a "real" MSR. > > Translating to a KVM-internal index is a hack to avoid having to plumb a 64-bit > index into all the MSR code. We could do that, i.e. pass the full kvm_x86_reg_id > into the MSR helpers, but I'm not convinced it'd be worth the churn. That said, > I'm not opposed to the idea either, if others prefer that approach. > > E.g. > > diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h > index 738c449e4f9e..21152796238a 100644 > --- a/arch/x86/include/uapi/asm/kvm.h > +++ b/arch/x86/include/uapi/asm/kvm.h > @@ -420,6 +420,8 @@ struct kvm_x86_reg_id { > __u16 rsvd16; > }; > > +#define MSR_KVM_GUEST_SSP 0 > + > #define KVM_SYNC_X86_REGS (1UL << 0) > #define KVM_SYNC_X86_SREGS (1UL << 1) > #define KVM_SYNC_X86_EVENTS (1UL << 2) > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index f45cdd9d8c1f..1a9e1e0c9f49 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -5990,6 +5990,19 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, > } > } > > +static int kvm_translate_synthetic_msr(u32 *index) > +{ > + switch (*index) { > + case MSR_KVM_GUEST_SSP: > + *index = MSR_KVM_INTERNAL_GUEST_SSP; > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > long kvm_arch_vcpu_ioctl(struct file *filp, > unsigned int ioctl, unsigned long arg) > { > diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h > index cc585051d24b..3b5a038f5260 100644 > --- a/arch/x86/kvm/x86.h > +++ b/arch/x86/kvm/x86.h > @@ -49,6 +49,15 @@ void kvm_spurious_fault(void); > #define KVM_FIRST_EMULATED_VMX_MSR MSR_IA32_VMX_BASIC > #define KVM_LAST_EMULATED_VMX_MSR MSR_IA32_VMX_VMFUNC > > +/* > + * KVM's internal, non-ABI indices for synthetic MSRs. The values themselves > + * are arbitrary and have no meaning, the only requirement is that they don't > + * conflict with "real" MSRs that KVM supports. Use values at the uppper end > + * of KVM's reserved paravirtual MSR range to minimize churn, i.e. these values > + * will be usable until KVM exhausts its supply of paravirtual MSR indices. > + */ > +#define MSR_KVM_INTERNAL_GUEST_SSP 0x4b564dff > + > #define KVM_DEFAULT_PLE_GAP 128 > #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 > #define KVM_DEFAULT_PLE_WINDOW_GROW 2 OK, I'll post an RFC patch for this change, thanks a lot!