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[147.75.48.161]) by mx.google.com with ESMTPS id b11-20020a63cf4b000000b00606dd49d3b5si12261467pgj.803.2024.05.08.03.02.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 03:02:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-173008-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of linux-kernel+bounces-173008-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-173008-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 61234B22CAD for ; Wed, 8 May 2024 10:00:34 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EF94179B96; Wed, 8 May 2024 10:00:27 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E392A3FE3F for ; Wed, 8 May 2024 10:00:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715162427; cv=none; b=dei9pXt5BoSKpBvRM3Ibv/0A7mAVRuI8XuWGqOgmaDxbJW9RyvfoJDpv/kCvQq4W63lhQdvTDulzi5PxigsR5e65rS+S2iKFIyaCwakgNJYi+DdrJKZMjaVpEVfo+DV88XUHLSap8dhH005LSUno/uE4GKJZzdOWRVcm2/b6uZ4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715162427; c=relaxed/simple; bh=Clksgg3nQKgJU4IUYhhUlpLCznOj3chtVCYbTOvxo4I=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=bXrg/5n+RzINbXPB++pQZn+23sIK1uL3QgP0WJiOij/DsLvMhH5/3tVxoZ5i0o5USCxthd/rrn3TsDjoM2MRWnGs+rw9nlNGeNa3bvvQ/HNA+ACXjWX8oGTTocwFglhxARx3HhmrNmwdHzhe/QHR8y7rwiWgohnE9xIe7kZ1RdA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 980B71063; Wed, 8 May 2024 03:00:49 -0700 (PDT) Received: from [10.163.34.220] (unknown [10.163.34.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EA6BA3F587; Wed, 8 May 2024 03:00:19 -0700 (PDT) Message-ID: <674dac6b-4fd5-4460-81fd-6b215b21434e@arm.com> Date: Wed, 8 May 2024 15:30:22 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/4] arm64/mm: Enable userfaultfd write-protect Content-Language: en-US To: Will Deacon , Ryan Roberts Cc: Catalin Marinas , Joey Gouly , Ard Biesheuvel , Mark Rutland , David Hildenbrand , Peter Xu , Mike Rapoport , Shivansh Vij , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20240503144604.151095-1-ryan.roberts@arm.com> <20240507110750.GA22289@willie-the-truck> From: Anshuman Khandual In-Reply-To: <20240507110750.GA22289@willie-the-truck> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/7/24 16:37, Will Deacon wrote: > Hi Ryan, > > On Fri, May 03, 2024 at 03:45:58PM +0100, Ryan Roberts wrote: >> This series adds uffd write-protect support for arm64. >> >> Previous attempts to add uffd-wp (and soft-dirty) have failed because of a >> perceived lack of available PTE SW bits. However it actually turns out that >> there are 2 available but they are hidden. PTE_PROT_NONE was previously >> occupying a SW bit, but can be moved, freeing up the SW bit. Bit 63 is marked as >> "IGNORED" in the Arm ARM, but it does not currently indicate "reserved for SW >> use" like it does for the other SW bits. I've confirmed with the spec owner that >> this is an oversight; the bit is intended to be reserved for SW use and the spec >> will clarify this in a future update. >> >> So now we have two spare bits; patch 4 enables uffd-wp on arm64, using the SW >> bit freed up by moving PTE_PROT_NONE. This leaves bit 63 spare for future use >> (e.g. soft-dirty - see RFC at [4] - or some other usage). >> >> --- >> >> This applies on top of v6.9-rc5. > > I chucked this into the CI on Friday and it looks to have survived the > long weekend, so I've gone ahead and merged it into for-next/core. Short > of any last minute failures (touch wood), this should land in 6.10. It would be great to have some memory migration tests (including THP and HugeTLB) thrown at this series, which should test the mapped, migration entry transitions etc. But not sure if there are any such tests off the shelf and readily available in the CI system.