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From: cong yang <yangcong5@huaqin.corp-partner.google.com>
Date: Wed, 8 May 2024 19:55:57 +0800
Message-ID: <CAHwB_NJHOphvydx8=HjgroE6ZXyJz-MHsJUwiedsMhshG0CMkQ@mail.gmail.com>
Subject: Re: [PATCH v4 5/7] drm/panel: himax-hx83102: Support for BOE
 nv110wum-l60 MIPI-DSI panel
To: Doug Anderson <dianders@chromium.org>
Cc: sam@ravnborg.org, neil.armstrong@linaro.org, daniel@ffwll.ch, 
	linus.walleij@linaro.org, krzysztof.kozlowski+dt@linaro.org, 
	robh+dt@kernel.org, conor+dt@kernel.org, airlied@gmail.com, 
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org, xuxinxiong@huaqin.corp-partner.google.com
Content-Type: text/plain; charset="UTF-8"
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Hi,

Doug Anderson <dianders@chromium.org> =E4=BA=8E2024=E5=B9=B45=E6=9C=888=E6=
=97=A5=E5=91=A8=E4=B8=89 07:35=E5=86=99=E9=81=93=EF=BC=9A
>
> Hi,
>
> On Tue, May 7, 2024 at 6:53=E2=80=AFAM Cong Yang
> <yangcong5@huaqin.corp-partner.google.com> wrote:
> >
> > +static int boe_nv110wum_init(struct hx83102 *ctx)
> > +{
> > +       struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }=
;
> > +
> > +       msleep(60);
> > +
> > +       hx83102_enable_extended_cmds(ctx, true);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, =
0xaf, 0xaf, 0x2b, 0xeb, 0x42,
> > +                                        0xe1, 0x4d, 0x36, 0x36, 0x36, =
0x36, 0x1a, 0x8b, 0x11, 0x65, 0x00,
> > +                                        0x88, 0xfa, 0xff, 0xff, 0x8f, =
0xff, 0x08, 0x9a, 0x33);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0=
x47, 0xb0, 0x80, 0x00, 0x12,
> > +                                        0x71, 0x3c, 0xa3, 0x11, 0x00, =
0x00, 0x00, 0x88, 0xf5, 0x22, 0x8f);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x49, 0x=
49, 0x32, 0x32, 0x14, 0x32,
> > +                                        0x84, 0x6e, 0x84, 0x6e, 0x01, =
0x9c);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x=
04);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20=
);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0=
x84);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x36, 0=
x36, 0x22, 0x00, 0x00, 0xa0,
> > +                                        0x61, 0x08, 0xf5, 0x03);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x=
1e, 0x30, 0xd4, 0x01);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, =
0x13, 0x07, 0x00, 0x0f, 0x34);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, =
0x03, 0x44);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03=
);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, =
0x06, 0x00, 0x02, 0x04, 0x0c, 0xff);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x1f=
, 0x11, 0x1f, 0x11);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0=
x00, 0x00, 0x00, 0x00, 0x04,
> > +                                        0x08, 0x04, 0x08, 0x37, 0x37, =
0x64, 0x4b, 0x11, 0x11, 0x03, 0x03, 0x32,
> > +                                        0x10, 0x0e, 0x00, 0x0e, 0x32, =
0x10, 0x0a, 0x00, 0x0a, 0x32, 0x17, 0x98,
> > +                                        0x07, 0x98, 0x00, 0x00);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0=
x18, 0x18, 0x18, 0x1e, 0x1e,
> > +                                        0x1e, 0x1e, 0x1f, 0x1f, 0x1f, =
0x1f, 0x24, 0x24, 0x24, 0x24, 0x07, 0x06,
> > +                                        0x07, 0x06, 0x05, 0x04, 0x05, =
0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00,
> > +                                        0x01, 0x00, 0x21, 0x20, 0x21, =
0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
> > +                                        0x18, 0x18);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaf, 0=
xaa, 0xaa, 0xaa, 0xaa, 0xa0,
> > +                                        0xaf, 0xaa, 0xaa, 0xaa, 0xaa, =
0xa0);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x00, 0x=
05, 0x0d, 0x14, 0x1b, 0x2c,
> > +                                        0x44, 0x49, 0x51, 0x4c, 0x67, =
0x6c, 0x71, 0x80, 0x7d, 0x84, 0x8d, 0xa0,
> > +                                        0xa0, 0x4f, 0x58, 0x64, 0x73, =
0x00, 0x05, 0x0d, 0x14, 0x1b, 0x2c, 0x44,
> > +                                        0x49, 0x51, 0x4c, 0x67, 0x6c, =
0x71, 0x80, 0x7d, 0x84, 0x8d, 0xa0, 0xa0,
> > +                                        0x4f, 0x58, 0x64, 0x73);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x07, 0x=
10, 0x10, 0x1a, 0x26, 0x9e,
> > +                                        0x00, 0x53, 0x9b, 0x14, 0x14);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x11=
, 0x00, 0x00, 0x89, 0x30, 0x80,
> > +                                        0x07, 0x80, 0x02, 0x58, 0x00, =
0x14, 0x02, 0x58, 0x02, 0x58, 0x02, 0x00,
> > +                                        0x02, 0x2c, 0x00, 0x20, 0x02, =
0x02, 0x00, 0x08, 0x00, 0x0c, 0x05, 0x0e,
> > +                                        0x04, 0x94, 0x18, 0x00, 0x10, =
0xf0, 0x03, 0x0c, 0x20, 0x00, 0x06, 0x0b,
> > +                                        0x0b, 0x33, 0x0e);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0=
xff, 0xff, 0xff, 0xfa, 0xa0,
> > +                                        0xff, 0xff, 0xff, 0xff, 0xfa, =
0xa0);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, =
0xbf, 0x11);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x96=
);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc9)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x84);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd1)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0xf6=
, 0x2b, 0x34, 0x2b, 0x74, 0x3b,
> > +                                        0x74, 0x6b, 0x74);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x=
00, 0x2b, 0x01, 0x7e, 0x0f,
> > +                                        0x7e, 0x10, 0xa0, 0x00, 0x00);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x02, 0x=
00, 0xbb, 0x11);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0=
xaf, 0xff, 0xff, 0xfa, 0xa0,
> > +                                        0xff, 0xaf, 0xff, 0xff, 0xfa, =
0xa0);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x=
01, 0xfe, 0x01, 0xfe, 0x01,
> > +                                        0x00, 0x00, 0x00, 0x23, 0x00, =
0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x65,
> > +                                        0x02, 0x01, 0x00, 0x00, 0x00, =
0x00, 0x00, 0x00, 0x01, 0x00);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0=
xaf, 0xaa, 0xaa, 0xa0, 0x00,
> > +                                        0xaa, 0xaf, 0xaa, 0xaa, 0xa0, =
0x00, 0xaa, 0xaf, 0xaa, 0xaa, 0xa0, 0x00,
> > +                                        0xaa, 0xaf, 0xaa, 0xaa, 0xa0, =
0x00);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0x=
ff, 0xf8);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x00=
);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f);
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f)=
;
> > +       mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
> > +       hx83102_enable_extended_cmds(ctx, false);
>
> It's not super important, but in panel drivers I converted to the
> mipi_dsi_dcs_write_seq_multi() I checked the "accum_err" and did an
> early return right before any mdelay() calls. This means that if any
> of the above failed then we didn't waste time with the mdelay().

Ok, I wiil add check accum_err before calling mdelay in V4.
Thanks.
>
> > +
> > +       msleep(50);
> > +
> > +       return dsi_ctx.accum_err;
> > +};