Received: by 2002:ab2:6991:0:b0:1f7:f6c3:9cb1 with SMTP id v17csp469191lqo; Wed, 8 May 2024 05:42:01 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCVAbLGCmKhOVPVuSCnab7b2ASCvIJSZUY+8Cur4xZkd7EW4tXayNKPTa1f6AZzC1/HhW7FZ7uWh5ly6wHj+5Tx7BS2IUCdqay2Trt2BAw== X-Google-Smtp-Source: AGHT+IFNbx5RD5yZxHZN3ZsnsBG1hie3tWjz+5HZF1oCrX00dCVJsKZxFIcfr3Yo1bX3AKsW4NKs X-Received: by 2002:a05:6a00:4d0e:b0:6f3:89d3:cae3 with SMTP id d2e1a72fcca58-6f49c23576bmr2544597b3a.16.1715172121450; Wed, 08 May 2024 05:42:01 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1715172121; cv=pass; d=google.com; s=arc-20160816; b=hCMOR33ZLe89aMdhVR+xBLfJ+KeOKesf3j8kZTKZGLpH2r4zOKUgVOc1B9SkHRM8VE ohIHTtCSdt54E5CR1700WTDiKwEF4JBB00phT4Fsvj4tIFpqm9gzwpJQ41/jZCMYVhoh EU09BDiYl8vR1joKiIUgAk7/ZBpTVQX+3Z0qUk7ykWKzm6yGC6m/A12FK43+9/zErelt GHPlJFQ1SNu9bBfkwN47o6Bl41yc2+K5GGFTjGj+RRjGQiF0W+KLwkWyUXOjM9emTg5g HtDQjPuWIS9yasnD100/UY4WIToRkEnRHTHbTxaCU9otm2274g2V0aPsKdexBarjtYX+ xAPg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from; bh=Ku3fm1Eea9nmC4NuWKjuSiPxJXalPnuM0q/NMTgeThc=; fh=dvR/tTWg2OfrU+TdVNug7ZowrURi76OJYRbHXzqKj5w=; b=FCkCB4vAnP79WaqvWGXge8ExplKM7G8b/PR+YfafCXRcboPp3AxrZC7A/b+BkDkdpw 3AVY+vFkJ92zGR12jvrfHzR65N/XxM/3PNa7O0q5yniAUCxh6QxVHfkvLX5YWxJ63qm3 bS3DtIv7iotJeislDIu97b0hNeWGEVnXPTJPnnoPET7G3tmD4DZThUI48D6arjf8J1WT FlWl4UhiwS+LN1iGSfjK+6oVhvi6pAs2Y9ly2UjRRRs0DjX3G0hvT3oYT/L/O/7JHVlP oEyossLzzyJFtIIFvOMyE6fVF5JJ6LWaw7j3a7ougLujJThjHYTB9gHUUtR8XODUTr8C 84NQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1 spf=pass spfdomain=realtek.com); spf=pass (google.com: domain of linux-kernel+bounces-173233-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-173233-linux.lists.archive=gmail.com@vger.kernel.org" Return-Path: Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id d4-20020a056a00244400b006f3ebe86ea5si8447787pfj.193.2024.05.08.05.42.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 05:42:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-173233-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=realtek.com); spf=pass (google.com: domain of linux-kernel+bounces-173233-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-173233-linux.lists.archive=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 168172835BE for ; Wed, 8 May 2024 12:42:01 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AD2B854FA3; Wed, 8 May 2024 12:41:52 +0000 (UTC) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 407173F8F6; Wed, 8 May 2024 12:41:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715172112; cv=none; b=E3+YDuBLfhBk1u/5TGwAsmi9KL1k9iBUd4sgdFoOFlxxREpD7dQGnu7lQ6Zxaw4afQ8oYXtot/RQaLs7RjuEZfBFk+aKuLqAxzHteERmmp+K22zUjsTa2BuIiRtimAHQyr7vNuSpcbeBCi7BBeZAk4QMokDE9I1c5AbS5KFww3s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715172112; c=relaxed/simple; bh=rNCzJoNgKfbdR0wgMkW1ZmVluRFxrOnzBc/iQXwKEoA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Q+ECD9owMvjc9sd4T3LGwfIj6Js2r6Mp8DM9Fzc5R9zBsqT/Ojq8Ce7w+KIctQkFH+PNAA1IiHLZlwRWWczVjaGkEm8mQ2yJr3a+VvFt/MNpaAIuG4YcWKlfqJycWShxU7XkSd4nnoc8IXWbd4tOgHPfWmJtLcudCkTGonShDmA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 448CfVzkD466284, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/2.95/5.92) with ESMTPS id 448CfVzkD466284 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 8 May 2024 20:41:31 +0800 Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Wed, 8 May 2024 20:41:32 +0800 Received: from RTDOMAIN (172.21.210.160) by RTEXMBS04.realtek.com.tw (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Wed, 8 May 2024 20:41:30 +0800 From: Justin Lai To: CC: , , , , , , , , , , Justin Lai Subject: [PATCH net-next v18 03/13] rtase: Implement the rtase_down function Date: Wed, 8 May 2024 20:39:35 +0800 Message-ID: <20240508123945.201524-4-justinlai0215@realtek.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240508123945.201524-1-justinlai0215@realtek.com> References: <20240508123945.201524-1-justinlai0215@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: RTEXH36505.realtek.com.tw (172.21.6.25) To RTEXMBS04.realtek.com.tw (172.21.6.97) Implement the rtase_down function to disable hardware setting and interrupt and clear descriptor ring. Signed-off-by: Justin Lai --- .../net/ethernet/realtek/rtase/rtase_main.c | 152 ++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/drivers/net/ethernet/realtek/rtase/rtase_main.c b/drivers/net/ethernet/realtek/rtase/rtase_main.c index 8fcfb53fbfda..d30dd9bbf09b 100644 --- a/drivers/net/ethernet/realtek/rtase/rtase_main.c +++ b/drivers/net/ethernet/realtek/rtase/rtase_main.c @@ -187,6 +187,57 @@ static void rtase_free_desc(struct rtase_private *tp) } } +static void rtase_unmap_tx_skb(struct pci_dev *pdev, u32 len, + struct rtase_tx_desc *desc) +{ + dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), len, + DMA_TO_DEVICE); + desc->opts1 = cpu_to_le32(RTK_OPTS1_DEBUG_VALUE); + desc->opts2 = 0x00; + desc->addr = cpu_to_le64(RTK_MAGIC_NUMBER); +} + +static void rtase_tx_clear_range(struct rtase_ring *ring, u32 start, u32 n) +{ + const struct rtase_private *tp = ring->ivec->tp; + struct rtase_tx_desc *desc_base = ring->desc; + struct net_device *dev = tp->dev; + u32 i; + + for (i = 0; i < n; i++) { + u32 entry = (start + i) % RTASE_NUM_DESC; + struct rtase_tx_desc *desc = desc_base + entry; + u32 len = ring->mis.len[entry]; + struct sk_buff *skb; + + if (len == 0) + continue; + + rtase_unmap_tx_skb(tp->pdev, len, desc); + ring->mis.len[entry] = 0; + skb = ring->skbuff[entry]; + if (!skb) + continue; + + dev->stats.tx_dropped++; + dev_kfree_skb_any(skb); + ring->skbuff[entry] = NULL; + } +} + +static void rtase_tx_clear(struct rtase_private *tp) +{ + struct rtase_ring *ring; + u16 i; + + for (i = 0; i < tp->func_tx_queue_num; i++) { + ring = &tp->tx_ring[i]; + rtase_tx_clear_range(ring, ring->dirty_idx, RTASE_NUM_DESC); + ring->cur_idx = 0; + ring->dirty_idx = 0; + } +} + static void rtase_mark_to_asic(union rtase_rx_desc *desc, u32 rx_buf_sz) { u32 eor = le32_to_cpu(desc->desc_cmd.opts1) & RTASE_RING_END; @@ -424,6 +475,80 @@ static void rtase_tally_counter_clear(const struct rtase_private *tp) rtase_w32(tp, RTASE_DTCCR0, cmd | RTASE_COUNTER_RESET); } +static void rtase_irq_dis_and_clear(const struct rtase_private *tp) +{ + const struct rtase_int_vector *ivec = &tp->int_vector[0]; + u32 val1; + u16 val2; + u8 i; + + rtase_w32(tp, ivec->imr_addr, 0); + val1 = rtase_r32(tp, ivec->isr_addr); + rtase_w32(tp, ivec->isr_addr, val1); + + for (i = 1; i < tp->int_nums; i++) { + ivec = &tp->int_vector[i]; + rtase_w16(tp, ivec->imr_addr, 0); + val2 = rtase_r16(tp, ivec->isr_addr); + rtase_w16(tp, ivec->isr_addr, val2); + } +} + +static void rtase_poll_timeout(const struct rtase_private *tp, u32 cond, + u32 sleep_us, u64 timeout_us, u16 reg) +{ + int err; + u8 val; + + err = read_poll_timeout(rtase_r8, val, val & cond, sleep_us, + timeout_us, false, tp, reg); + + if (err == -ETIMEDOUT) + netdev_err(tp->dev, "poll reg 0x00%x timeout\n", reg); +} + +static void rtase_nic_reset(const struct net_device *dev) +{ + const struct rtase_private *tp = netdev_priv(dev); + u16 rx_config; + u8 val; + + rx_config = rtase_r16(tp, RTASE_RX_CONFIG_0); + rtase_w16(tp, RTASE_RX_CONFIG_0, rx_config & ~RTASE_ACCEPT_MASK); + + val = rtase_r8(tp, RTASE_MISC); + rtase_w8(tp, RTASE_MISC, val | RTASE_RX_DV_GATE_EN); + + val = rtase_r8(tp, RTASE_CHIP_CMD); + rtase_w8(tp, RTASE_CHIP_CMD, val | RTASE_STOP_REQ); + mdelay(2); + + rtase_poll_timeout(tp, RTASE_STOP_REQ_DONE, 100, 150000, + RTASE_CHIP_CMD); + + rtase_poll_timeout(tp, RTASE_TX_FIFO_EMPTY, 100, 100000, + RTASE_FIFOR); + + rtase_poll_timeout(tp, RTASE_RX_FIFO_EMPTY, 100, 100000, + RTASE_FIFOR); + + val = rtase_r8(tp, RTASE_CHIP_CMD); + rtase_w8(tp, RTASE_CHIP_CMD, val & ~(RTASE_TE | RTASE_RE)); + val = rtase_r8(tp, RTASE_CHIP_CMD); + rtase_w8(tp, RTASE_CHIP_CMD, val & ~RTASE_STOP_REQ); + + rtase_w16(tp, RTASE_RX_CONFIG_0, rx_config); +} + +static void rtase_hw_reset(const struct net_device *dev) +{ + const struct rtase_private *tp = netdev_priv(dev); + + rtase_irq_dis_and_clear(tp); + + rtase_nic_reset(dev); +} + static void rtase_nic_enable(const struct net_device *dev) { const struct rtase_private *tp = netdev_priv(dev); @@ -527,6 +652,33 @@ static int rtase_open(struct net_device *dev) return ret; } +static void rtase_down(struct net_device *dev) +{ + struct rtase_private *tp = netdev_priv(dev); + struct rtase_int_vector *ivec; + struct rtase_ring *ring, *tmp; + u32 i; + + for (i = 0; i < tp->int_nums; i++) { + ivec = &tp->int_vector[i]; + napi_disable(&ivec->napi); + list_for_each_entry_safe(ring, tmp, &ivec->ring_list, + ring_entry) { + list_del(&ring->ring_entry); + } + } + + netif_tx_disable(dev); + + netif_carrier_off(dev); + + rtase_hw_reset(dev); + + rtase_tx_clear(tp); + + rtase_rx_clear(tp); +} + static int rtase_close(struct net_device *dev) { struct rtase_private *tp = netdev_priv(dev); -- 2.34.1