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Date: Wed, 08 May 2024 07:53:44 -0700 (PDT)
Subject:     Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT
In-Reply-To: <CAEEQ3wnthxGbrJ_qLnZUQ9w3E_1UWgMign5P=+rNP2p5xGm4Bg@mail.gmail.com>
CC: Conor Dooley <conor@kernel.org>, rafael@kernel.org, lenb@kernel.org,
  linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley <paul.walmsley@sifive.com>,
  aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, bhelgaas@google.com, james.morse@arm.com,
  jhugo@codeaurora.org, jeremy.linton@arm.com, john.garry@huawei.com, Jonathan.Cameron@huawei.com,
  pierre.gondois@arm.com, sudeep.holla@arm.com, tiantao6@huawei.com
From: Palmer Dabbelt <palmer@dabbelt.com>
To: cuiyunhui@bytedance.com, Sunil V L <sunilvl@ventanamicro.com>
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On Wed, 08 May 2024 04:19:01 PDT (-0700), cuiyunhui@bytedance.com wrote:
> Hi Palmer,
>
> Gentle ping...

+Sunil, as he's the ACPI/RISC-V maintainer and I generally wait for his 
review on this stuff.

>
> On Fri, May 3, 2024 at 12:37 AM Conor Dooley <conor@kernel.org> wrote:
>>
>> On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
>> > Before cacheinfo can be built correctly, we need to initialize level
>> > and type. Since RSIC-V currently does not have a register group that
>> > describes cache-related attributes like ARM64, we cannot obtain them
>> > directly, so now we obtain cache leaves from the ACPI PPTT table
>> > (acpi_get_cache_info()) and set the cache type through split_levels.
>> >
>> > Suggested-by: Jeremy Linton <jeremy.linton@arm.com>
>> > Suggested-by: Sudeep Holla <sudeep.holla@arm.com>
>> : Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
>>
>> I'm not an ACPI head, so whether or not the table is valid on RISC-V or
>> w/e I do not know, but the code here looks sane to me, so
>
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>>
>> Cheers,
>> Conor.
>
> Thanks,
> Yunhui