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Wed, 8 May 2024 15:16:23 GMT Received: from smtprelay05.dal12v.mail.ibm.com ([172.16.1.7]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3xysgsdcgw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 May 2024 15:16:23 +0000 Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay05.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 448FGFfi23200272 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 8 May 2024 15:16:17 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E8BE758060; Wed, 8 May 2024 15:16:14 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C37975805C; Wed, 8 May 2024 15:16:14 +0000 (GMT) Received: from [9.61.25.238] (unknown [9.61.25.238]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Wed, 8 May 2024 15:16:14 +0000 (GMT) Message-ID: Date: Wed, 8 May 2024 10:16:14 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] hwmon: (ucd90320) Increase delay from 250 to 500us To: Lakshmi Yadlapati , jdelvare@suse.com, linux@roeck-us.net Cc: ninad@linux.ibm.com, linux-kernel@vger.kernel.org References: <20240507194603.1305750-1-lakshmiy@us.ibm.com> Content-Language: en-US From: Eddie James In-Reply-To: <20240507194603.1305750-1-lakshmiy@us.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: YQJ3gLj7ikHBfaduKTxWf34CZn-pFDnv X-Proofpoint-GUID: YQJ3gLj7ikHBfaduKTxWf34CZn-pFDnv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-08_09,2024-05-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=979 suspectscore=0 clxscore=1011 malwarescore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405080109 On 5/7/24 14:46, Lakshmi Yadlapati wrote: > Following the failure observed with a delay of 250us, experiments were > conducted with various delays. It was found that a delay of 350us > effectively mitigated the issue. > > To provide a more optimal solution while still allowing a margin for > stability, the delay is being adjusted to 500us. Reviewed-by: Eddie James > > Signed-off-by: Lakshmi Yadlapati > --- > drivers/hwmon/pmbus/ucd9000.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwmon/pmbus/ucd9000.c b/drivers/hwmon/pmbus/ucd9000.c > index 8d9d422450e5..d817c719b90b 100644 > --- a/drivers/hwmon/pmbus/ucd9000.c > +++ b/drivers/hwmon/pmbus/ucd9000.c > @@ -80,11 +80,11 @@ struct ucd9000_debugfs_entry { > * It has been observed that the UCD90320 randomly fails register access when > * doing another access right on the back of a register write. To mitigate this > * make sure that there is a minimum delay between a write access and the > - * following access. The 250us is based on experimental data. At a delay of > - * 200us the issue seems to go away. Add a bit of extra margin to allow for > + * following access. The 500 is based on experimental data. At a delay of > + * 350us the issue seems to go away. Add a bit of extra margin to allow for > * system to system differences. > */ > -#define UCD90320_WAIT_DELAY_US 250 > +#define UCD90320_WAIT_DELAY_US 500 > > static inline void ucd90320_wait(const struct ucd9000_data *data) > {