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From: Shengjiu Wang <shengjiu.wang@nxp.com>
To: robh@kernel.org,
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Subject: [PATCH 1/2] arm64: dts: imx8mp: Initialize audio PLLs from audiomix subsystem
Date: Thu,  9 May 2024 13:14:57 +0800
Message-Id: <1715231698-451-2-git-send-email-shengjiu.wang@nxp.com>
In-Reply-To: <1715231698-451-1-git-send-email-shengjiu.wang@nxp.com>
References: <1715231698-451-1-git-send-email-shengjiu.wang@nxp.com>
Precedence: bulk

Initialize audio PLL1 as the parent clock for 8kHz series rates,
audio PLL2 as the parent clock for 11kHz series rates. that PLL1
and PLL2 can together support full range of audio sample rates.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index b92abb5a5c53..459c4a54d30e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1579,6 +1579,9 @@ audio_blk_ctrl: clock-controller@30e20000 {
 					      "sai1", "sai2", "sai3",
 					      "sai5", "sai6", "sai7";
 				power-domains = <&pgc_audio>;
+				assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>,
+						  <&clk IMX8MP_AUDIO_PLL2>;
+				assigned-clock-rates = <393216000>, <361267200>;
 			};
 		};
 
-- 
2.34.1