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Message-ID: <cb905f6f-9d88-4ea7-f4c7-5b0baaf8290d@quicinc.com>
Date: Thu, 9 May 2024 16:14:58 +0530
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Subject: Re: [PATCH v2] clk: qcom: gcc-ipq9574: Add BRANCH_HALT_VOTED flag
To: Stephen Boyd <sboyd@kernel.org>, <andersson@kernel.org>,
        <bhupesh.sharma@linaro.org>, <linux-arm-msm@vger.kernel.org>,
        <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <mturquette@baylibre.com>, <quic_anusha@quicinc.com>
CC: <quic_srichara@quicinc.com>, <quic_varada@quicinc.com>,
        <stable@vger.kernel.org>
References: <20240506063751.346759-1-quic_mdalam@quicinc.com>
 <ee18e89b77f0c08ef45cbcc75e2361bf.sboyd@kernel.org>
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From: Md Sadre Alam <quic_mdalam@quicinc.com>
In-Reply-To: <ee18e89b77f0c08ef45cbcc75e2361bf.sboyd@kernel.org>
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On 5/7/2024 5:34 AM, Stephen Boyd wrote:
> Quoting Md Sadre Alam (2024-05-05 23:37:51)
>> Add BRANCH_HALT_VOTED flag to inform clock framework
>> don't check for CLK_OFF bit.
>>
>> CRYPTO_AHB_CLK_ENA and CRYPTO_AXI_CLK_ENA enable bit is
>> present in other VOTE registers also, like TZ.
>> If anyone else also enabled this clock, even if we turn
>> off in GCC_APCS_CLOCK_BRANCH_ENA_VOTE | 0x180B004, it won't
>> turn off.
>> Also changes the CRYPTO_AHB_CLK_ENA & CRYPTO_AXI_CLK_ENA
>> offset to 0xb004 from 0x16014.
> 
> How about this?
> 
>   The crypto_ahb and crypto_axi clks are hardware voteable. This means
>   that the halt bit isn't reliable because some other voter in the
>   system, e.g. TrustZone, could be keeping the clk enabled when the
>   kernel turns it off from clk_disable(). Make these clks use voting mode
>   by changing the halt check to BRANCH_HALT_VOTED and toggle the voting
>   bit in the voting register instead of directly controlling the branch
>   by writing to the branch register. This fixes stuck clk warnings seen
>   on ipq9574 and saves power by actually turning the clk off.

  Ok , will update commit message in next patch.
> 
>>
>> Cc: stable@vger.kernel.org
>> Fixes: f6b2bd9cb29a ("clk: qcom: gcc-ipq9574: Enable crypto clocks")
>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>