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AJvYcCX4OHTIFB36QbmVYmwiPxz3KI5fD0wy89FlnY3jYvt5isbvjvzQ9Lg6GIfMY82gsgLmoDO6xP//ToyvzRAIRXjvAoK4De0eUZL6/40+/qvelwjPuFysWben0ZUn36SluRH+9o2go6LPR8eogp/N3hN4H5/LoNyCd8EmeeqHLw2b1961dQ== X-Gm-Message-State: AOJu0Yz2HMMSp2qcWM3+F2znz201XjJW90RY2oopfg0v222ymu2DYmYB K5upoSYEDLPKWJ9wDg/wfWyY3DcRIsf4PvNAC3z0QNog2YnLx88= X-Received: by 2002:a05:600c:348c:b0:41c:1434:f571 with SMTP id 5b1f17b1804b1-41f71ad0a6amr46179165e9.37.1715256441686; Thu, 09 May 2024 05:07:21 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccce1912sm24112005e9.11.2024.05.09.05.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 05:07:21 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v2 0/7] Add DSI support for RK3128 Date: Thu, 9 May 2024 14:07:08 +0200 Message-ID: <20240509120715.86694-1-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series aims to add support for the DesignWare MIPI DSI controller and the Innoslicon D-PHY found in RK3128 SoCs. The code additions are rather tiny: It only need some code in the Rockchip dw-mipi-dsi glue layer for this SoC, add support for an additional clock and do some changes in the SoC's clock driver. Support for the phy was already added when the Innosilicon D-PHY driver was initially submitted. I tested it with a 800x1280 DSI panel where all 4 lanes that are supported are used. changes in v2: To improve power-efficiency when the DSI controller is not in use, I dropped the patch which made hclk_vio_h2p a critical clock and instead added support for an AHB clock to the DSI controller driver and updated the bindings and the addition to the SoC DT accordingly. Link to v1: https://lore.kernel.org/linux-kernel/20240506194343.282119-1-knaerzche@gmail.com/ Please see individual patches for details about the changes. Alex Bee (7): dt-bindings: display: rockchip,dw-mipi-dsi: Document RK3128 DSI dt-bindings: clock: rk3128: Add PCLK_MIPIPHY clk: rockchip: rk3128: Export PCLK_MIPIPHY drm/rockchip: dsi: Support optional AHB clock drm/rockchip: dsi: Add support for RK3128 ARM: dts: rockchip: Add D-PHY for RK3128 ARM: dts: rockchip: Add DSI for RK3128 .../rockchip/rockchip,dw-mipi-dsi.yaml | 25 +++++++++- arch/arm/boot/dts/rockchip/rk3128.dtsi | 50 +++++++++++++++++++ drivers/clk/rockchip/clk-rk3128.c | 2 +- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 45 +++++++++++++++++ include/dt-bindings/clock/rk3128-cru.h | 1 + 5 files changed, 121 insertions(+), 2 deletions(-) -- 2.43.2