Received-SPF: pass (google.com: domain of linux-kernel+bounces-174510-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
Message-ID: <1190cfb6-e2d1-4910-ad57-f7566343ff19@gmail.com>
Date: Thu, 9 May 2024 14:43:34 +0200
Precedence: bulk
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v2 0/7] Add DSI support for RK3128
To: =?UTF-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>,
 Andy Yan <andy.yan@rock-chips.com>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
 linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org,
 linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
 sebastian.reichel@collabora.com, Sandy Huang <hjc@rock-chips.com>,
 Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Daniel Vetter <daniel@ffwll.ch>, Maxime Ripard <mripard@kernel.org>,
 Conor Dooley <conor+dt@kernel.org>, Rob Herring <robh@kernel.org>,
 Thomas Zimmermann <tzimmermann@suse.de>, David Airlie <airlied@gmail.com>,
 Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>
References: <20240509120715.86694-1-knaerzche@gmail.com>
 <38423821.XM6RcZxFsP@diego>
Content-Language: en-US
From: Alex Bee <knaerzche@gmail.com>
In-Reply-To: <38423821.XM6RcZxFsP@diego>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 8bit

Hi Heiko

Am 09.05.24 um 14:21 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Donnerstag, 9. Mai 2024, 14:07:08 CEST schrieb Alex Bee:
>> This series aims to add support for the DesignWare MIPI DSI controller and
>> the Innoslicon D-PHY found in RK3128 SoCs. The code additions are rather
>> tiny: It only need some code in the Rockchip dw-mipi-dsi glue layer for
>> this SoC, add support for an additional clock and do some changes in the
>> SoC's clock driver. Support for the phy was already added when the
>> Innosilicon D-PHY driver was initially submitted. I tested it with a
>> 800x1280 DSI panel where all 4 lanes that are supported are used.
>>
>> changes in v2:
>>    To improve power-efficiency when the DSI controller is not in use, I
>>    dropped the patch which made hclk_vio_h2p a critical clock and instead
>>    added support for an AHB clock to the DSI controller driver and updated
>>    the bindings and the addition to the SoC DT accordingly.
> The naming already suggests that hclk_vio_h2p is not a clock-part of
> the actual dsi controller, but more an internal thing inside the clock
> controller.
>
> At least naming and perceived functionality would suggest a chain of
> 	hclk_vio -> hclk_vio_h2p -> pclk_mipi
I personally wouldn't give to much on naming when it comes to Rockchip
CRUs. Actually looking at "Fig. 2-5 Chip Clock Architecture Diagram 4" of
RK312x its:


.. -> hclk_vio

                    -> hclk_h2p (clock in question)
                    -> pclk_mipi (DSI APB clock)
                    -> hclk_rga
                    -> hclk_vop
                    ....

Also there is no other display output path (HDMI, LVDS) which requires this
clock to be enabled. They all work when it's disabled. That really makes me
think it's just the AHB clock line for the DSI controller. Maybe Andy can
share some details?

Alex

> In any case, I really don't see hclk_vio_h2p to be in the realm of the
> actual DSI controller, but more a part of clock-controller / interconnect.
> Similar to the NIU clocks for the interconnect.
>
> rk3588 actually tries to implement this already and while the
> gate-link clocks are described as "recent", I think this definitly the same
> concept used a most/all older Rockchip SoCs, just nobody cared about that
> till now ;-) [0] .
>
> So TL;DR I'd really prefer to not leak CRU-details into the DSI controller.
>
>
> Heiko
>
> [0] Which reminds me that I should look at Sebastian's make GATE-LINK
> actually-work-patch.
>
>
>
>