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AJvYcCXxDHUtZJtswUwqrMTWXAN3uUBMlIgEyOc5RO1J6tpxJsWjTg4ZpRAR5Icp4ghJdCB7A/Fu+CdUGs2Xs0UsOUHlbYT0CdLmsTTeUX+7tjsch6iIegC9awzsQMm1Vnz3x0QsG/eEevQyMx9KLiTQ7vQFMVEEgaZJk71zOzUb7v1cnaLJqQ== X-Gm-Message-State: AOJu0Yw5Sh+yb9HCejBgUug77RkDQ6Bwk+wSyVH25L/Pl8eONLeOP6j1 MkBR+hDhiMasAvA46yNdOeZe+djDvTsqgIeF6JRKWT/cc/sdeF8= X-Received: by 2002:a05:600c:4f0c:b0:41a:8b39:8040 with SMTP id 5b1f17b1804b1-41f71ec26d4mr53830265e9.20.1715263616318; Thu, 09 May 2024 07:06:56 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baad058sm1793311f8f.66.2024.05.09.07.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 07:06:55 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v3 0/7] Add DSI support for RK3128 Date: Thu, 9 May 2024 16:06:46 +0200 Message-ID: <20240509140653.168591-1-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series aims to add support for the DesignWare MIPI DSI controller and the Innoslicon D-PHY found in RK3128 SoCs. The code additions are rather tiny: It only need some code in the Rockchip dw-mipi-dsi glue layer for this SoC and do some changes in the SoC's clock driver. Support for the phy was already added when the Innosilicon D-PHY driver was initially submitted. I tested it with a 800x1280 DSI panel where all 4 lanes that are supported are used. changes in v2: To improve power-efficiency when the DSI controller is not in use, I dropped the patch which made hclk_vio_h2p a critical clock and instead added support for an AHB clock to the DSI controller driver and updated the bindings and the addition to the SoC DT accordingly. Link to v1: https://lore.kernel.org/linux-kernel/20240506194343.282119-1-knaerzche@gmail.com/ changes in v3: Dropped the changes for the additional AHB clock for the DSI controller, as it's not part of the IP block. (Heiko) Link to v2: https://lore.kernel.org/linux-kernel/20240509120715.86694-1-knaerzche@gmail.com/ Please see individual patches for details about the changes. Alex Bee (7): dt-bindings: display: rockchip,dw-mipi-dsi: Document RK3128 DSI dt-bindings: clock: rk3128: Add PCLK_MIPIPHY clk: rockchip: rk3128: Export PCLK_MIPIPHY clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks drm/rockchip: dsi: Add support for RK3128 ARM: dts: rockchip: Add D-PHY for RK3128 ARM: dts: rockchip: Add DSI for RK3128 .../rockchip/rockchip,dw-mipi-dsi.yaml | 2 + arch/arm/boot/dts/rockchip/rk3128.dtsi | 50 +++++++++++++++++++ drivers/clk/rockchip/clk-rk3128.c | 3 +- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 ++++++++ include/dt-bindings/clock/rk3128-cru.h | 1 + 5 files changed, 75 insertions(+), 1 deletion(-) -- 2.43.2