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Message-ID: <0fc91b47-5169-4f30-84fc-c6c4ac2718e2@broadcom.com>
Date: Thu, 9 May 2024 14:38:56 -0700
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Subject: Re: [PATCH v4 1/4] mips: bmips: rework and cache CBR addr handling
To: Christian Marangi <ansuelsmth@gmail.com>,
 Hauke Mehrtens <hauke@hauke-m.de>, =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=
 <zajec5@gmail.com>, Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
 Rob Herring <robh@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Conor Dooley <conor+dt@kernel.org>,
 Broadcom internal kernel review list
 <bcm-kernel-feedback-list@broadcom.com>, linux-mips@vger.kernel.org,
 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20240509204750.1538-1-ansuelsmth@gmail.com>
 <20240509204750.1538-2-ansuelsmth@gmail.com>
From: Florian Fainelli <florian.fainelli@broadcom.com>
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In-Reply-To: <20240509204750.1538-2-ansuelsmth@gmail.com>
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On 5/9/24 13:47, Christian Marangi wrote:
> Rework the handling of the CBR address and cache it. This address
> doesn't change and can be cached instead of reading the register every
> time.
> 
> This is in preparation of permitting to tweak the CBR address in DT with
> broken SoC or bootloader.
> 
> bmips_cbr_addr is defined in smp-bmips.c to keep compatibility with
> legacy brcm47xx/brcm63xx and generic BMIPS target.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
-- 
Florian


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