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b=bQTxF4iLMWEhk+YhPOzo0TzIeqi4dY9PMfaJhtRxlzi2cd1BYGtNy8LBpne+7ROsYsNgywl0aChJgNFfG469Ub0As/Y6hUHNQtLyzAAHLydbEhmoWQHMxM4IunoNTZHfhrvsxemiYPJMggg+dIPDdHMADFdlZ/5ZKY2xdwqcNzs= Received: from CYYPR12MB8655.namprd12.prod.outlook.com (2603:10b6:930:c4::19) by IA1PR12MB7615.namprd12.prod.outlook.com (2603:10b6:208:428::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.54; Sat, 11 May 2024 06:54:54 +0000 Received: from CYYPR12MB8655.namprd12.prod.outlook.com ([fe80::7fa2:65b3:1c73:cdbf]) by CYYPR12MB8655.namprd12.prod.outlook.com ([fe80::7fa2:65b3:1c73:cdbf%6]) with mapi id 15.20.7544.047; Sat, 11 May 2024 06:54:54 +0000 From: "Yuan, Perry" To: "Du, Xiaojian" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" CC: "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "hpa@zytor.com" , "daniel.sneddon@linux.intel.com" , "jpoimboe@kernel.org" , "pawan.kumar.gupta@linux.intel.com" , "Das1, Sandipan" , "kai.huang@intel.com" , "x86@kernel.org" , "Huang, Ray" , "rafael@kernel.org" , "Limonciello, Mario" Subject: RE: [PATCH 2/2] cpufreq: amd-pstate: change cpu freq transition delay for some models Thread-Topic: [PATCH 2/2] cpufreq: amd-pstate: change cpu freq transition delay for some models Thread-Index: AQHamgNtWe1ddAFBQ0WH2YyUktcGtLGRq5pw Date: Sat, 11 May 2024 06:54:54 +0000 Message-ID: References: <20240429070322.999500-1-Xiaojian.Du@amd.com> <20240429070322.999500-2-Xiaojian.Du@amd.com> In-Reply-To: <20240429070322.999500-2-Xiaojian.Du@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_ActionId=f834a747-db91-4a5f-9610-fa2faf9be99a;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_ContentBits=0;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_Enabled=true;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_Method=Standard;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_Name=General;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_SetDate=2024-05-11T06:52:39Z;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_SiteId=3dd8961f-e488-4e60-8e11-a82d994e183d; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CYYPR12MB8655.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8128357a-05e5-4309-54f1-08dc7187432f X-MS-Exchange-CrossTenant-originalarrivaltime: 11 May 2024 06:54:54.1069 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: gAE51TPd8nfl3T4c+pHecWEEXbHYJqzgSzB/yIxbFgPoTIPif7+lKCL2mlxOk7SSW9tmXCsG/+U0ikakmzgBPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7615 [AMD Official Use Only - General] > -----Original Message----- > From: Du, Xiaojian > Sent: Monday, April 29, 2024 3:03 PM > To: linux-kernel@vger.kernel.org; linux-pm@vger.kernel.org > Cc: tglx@linutronix.de; mingo@redhat.com; bp@alien8.de; > dave.hansen@linux.intel.com; hpa@zytor.com; > daniel.sneddon@linux.intel.com; jpoimboe@kernel.org; > pawan.kumar.gupta@linux.intel.com; Das1, Sandipan > ; kai.huang@intel.com; Yuan, Perry > ; x86@kernel.org; Huang, Ray > ; rafael@kernel.org; Du, Xiaojian > ; Limonciello, Mario > Subject: [PATCH 2/2] cpufreq: amd-pstate: change cpu freq transition dela= y > for some models > > Some of AMD ZEN4 APU/CPU have support for adjusting the CPU core clock > more quickly and presicely according to CPU work loading. > This is advertised by the Fast CPPC x86 feature. > This change will only be effective in the *passive mode* of AMD pstate > driver. From the test results of different transition delay values, 600us= is > chosen to make a balance between performance and power consumption. > > Some test results on AMD Ryzen 7840HS(Phoenix) APU: > > 1. Tbench > (Energy less is better, Throughput more is better, PPW--Performance per > Watt more is better) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Trans Delay Tbench governor:schedutil, 3-iterations avera= ge > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > 1000us Clients 1 2 4 = 8 12 16 > 32 > Energy/Joules 2010 2804 8768 = 17171 16170 > 15132 15027 > Throughput/(MB/s) 114 259 1041 = 3010 3135 > 4851 4605 > PPW 0.0567 0.0923 0.1187 = 0.1752 0.1938 > 0.3205 0.3064 > 600us Clients 1 2 4 = 8 12 16 32 > Energy/Joules 2115 (5.22%) 2388 (-14.84%) 10700(2= 2.03%) 16716 > (-2.65%) 15939 (-1.43%) 15053 (-0.52%) 15083 (0.37% ) > Throughput/(MB/s) 122 (7.02%) 234 (-9.65% ) 1188 (1= 4.12%) 3003 > (-0.23%) 3143 (0.26% ) 4842 (-0.19%) 4603 (-0.04%) > PPW 0.0576(1.59%) 0.0979(6.07% ) 0.111(-= 6.49%) > 0.1796(2.51% ) 0.1971(1.70% ) 0.3216(0.34% ) 0.3051(-0.42%) > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > 2.Dbench > (Energy less is better, Throughput more is better, PPW--Performance per > Watt more is better) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Trans Delay Dbench governor:schedutil, 3-iterations avera= ge > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > 1000us Clients 1 2 4 = 8 12 16 > 32 > Energy/Joules 4890 3779 3567 = 5157 5611 > 6500 8163 > Throughput/(MB/s) 327 167 220 = 577 775 > 938 1397 > PPW 0.0668 0.0441 0.0616 = 0.1118 0.1381 > 0.1443 0.1711 > 600us Clients 1 2 4 = 8 12 16 32 > Energy/Joules 4915 (0.51%) 4912 (29.98%) 3506 (-= 1.71%) 4907 (- > 4.85% ) 5011 (-10.69%) 5672 (-12.74%) 8141 (-0.27%) > Throughput/(MB/s) 348 (6.42%) 284 (70.06%) 220 (0= 00% ) 518 (- > 10.23%) 712 (-8.13% ) 854 (-8.96% ) 1475 (5.58% ) > PPW 0.0708(5.99%) 0.0578(31.07%) 0.0627(1= 79% ) 0.1055(- > 5.64% ) 0.142(2.82% ) 0.1505(4.30% ) 0.1811(5.84% ) > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > 3.Hackbench(less time is better) > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D > hackbench governor:schedutil > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D > Trans Delay Process Mode Ave time(s) Thread Mode Ave time(s) > 1000us 14.484 14.484 > 600us 14.418(-0.46%) 15.41(+6.39%) > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D > > 4.Perf_sched_bench(less time is better) > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D > Trans Delay perf_sched_bench governor:schedutil > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D > 1000us Groups 1 2 4 = 8 12 24 > AveTime(s) 1.64 2.851 5.878 = 11.636 16.093 > 26.395 > 600us Groups 1 2 4 = 8 12 24 > AveTime(s) 1.69(3.05%) 2.845(-0.21%) 5.843(-0.6= 0%) 11.576(- > 0.52%) 16.092(-0.01%) 26.32(-0.28%) > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D > > 5.Sysbench(higher is better) > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > Sysbench governor:schedutil > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > 1000us Thread 1 2 4 = 8 12 24 > Ave events 6020.98 12273.39 24119.8= 2 46171.57 > 47074.37 47831.72 > 600us Thread 1 2 4 = 8 12 24 > Ave events 6154.82(2.22%) 12271.63(-0.01%) 24392.5= (1.13%) > 46117.64(-0.12%) 46852.19(-0.47%) 47678.92(-0.32%) > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > > In conclusion, a shorter transition delay of cpu clock will make a quite = positive > effect to improve PPW on Dbench test, in the meanwhile , keep stable > performance on Tbench, Hackbench, Perf_sched_bench and Sysbench. > > Signed-off-by: Xiaojian Du > Reviewed-by: Mario Limonciello > --- > drivers/cpufreq/amd-pstate.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 2015c9fcc3c9..8c8594f67af6 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -50,6 +50,7 @@ > > #define AMD_PSTATE_TRANSITION_LATENCY 20000 > #define AMD_PSTATE_TRANSITION_DELAY 1000 > +#define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600 > #define AMD_PSTATE_PREFCORE_THRESHOLD 166 > > /* > @@ -868,7 +869,11 @@ static int amd_pstate_cpu_init(struct cpufreq_policy > *policy) > } > > policy->cpuinfo.transition_latency =3D > AMD_PSTATE_TRANSITION_LATENCY; > - policy->transition_delay_us =3D AMD_PSTATE_TRANSITION_DELAY; > + > + if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC)) > + policy->transition_delay_us =3D > AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY; > + else > + policy->transition_delay_us =3D > AMD_PSTATE_TRANSITION_DELAY; > > policy->min =3D min_freq; > policy->max =3D max_freq; > -- > 2.34.1 LGTM Reviewed-by: Perry Yuan