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Sat, 11 May 2024 03:02:56 +0000 From: Xingyu Wu To: Conor Dooley CC: Michael Turquette , Stephen Boyd , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "devicetree@vger.kernel.org" Subject: RE: [PATCH v5 0/2] Add notifier for PLL0 clock and set it 1.5GHz on Thread-Topic: [PATCH v5 0/2] Add notifier for PLL0 clock and set it 1.5GHz on Thread-Index: AQHaoEtCPDK2HwhwXUSWjcDZE/pIQ7GQ+umAgABXAkA= Date: Sat, 11 May 2024 03:02:56 +0000 Message-ID: References: <20240507065319.274976-1-xingyu.wu@starfivetech.com> <20240510-unfounded-syrup-d1263d57d05a@spud> In-Reply-To: <20240510-unfounded-syrup-d1263d57d05a@spud> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: NTZPR01MB0956:EE_|NTZPR01MB1113:EE_ x-ms-office365-filtering-correlation-id: 0a7f2ce1-10d1-4a7e-96c6-08dc7166db6a x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-Network-Message-Id: 0a7f2ce1-10d1-4a7e-96c6-08dc7166db6a X-MS-Exchange-CrossTenant-originalarrivaltime: 11 May 2024 03:02:56.1492 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: BX4E6/8rlyJExq4/kQd0xRCVAlcUEBhuB3CvLspPwdrkRZyx0qP87oBHYd57TV379L/JOxbkxz6z3KTfuXkkOuWwXOTUunsQPySbetbLE1o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: NTZPR01MB1113 On 11/05/2024 05:05, Conor Dooley wrote: >=20 > On Tue, May 07, 2024 at 02:53:17PM +0800, Xingyu Wu wrote: > > This patch is to add the notifier for PLL0 clock and set the PLL0 rate > > to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC. > > > > The first patch is to add the notifier for PLL0 clock. Setting the > > PLL0 rate need the son clock (cpu_root) to switch its parent clock to > > OSC clock and switch it back after setting PLL0 rate. It need to use > > the cpu_root clock from SYSCRG and register the notifier in the SYSCRG > > driver. > > > > The second patch is to set cpu_core rate to 500MHz and PLL0 rate to > > 1.5GHz to fix the problem about the lower rate of CPUfreq on the > > visionfive board. The cpu_core clock rate is set to 500MHz first to > > ensure that the cpu frequency will not suddenly become high and the > > cpu voltage is not enough to cause a crash when the PLL0 is set to 1.5G= Hz. > > The cpu voltage and frequency are then adjusted together by CPUfreq. >=20 > Hmm, how does sequencing work here? If we split the patches between trees= it > sounds like without the dts patch, the clock tree would (or > could) crash, or mainline if the clock changes there before the dts ones = do. Am I > misunderstanding that? Oh, I think you misunderstood it. Patch 1 (clock driver patch) does not cau= se the clock tree crash without the patch 2 (dts patch), and it just provides the = correct flow of how to change the PLL0 rate. The patch 2 is to set the clock rate o= f cpu_core and PLL0 rate, which causes the crash without patch 1. Setting cpu= _core rate is to avoid crashes by insufficient cpu voltage when setting PLL0 rate= . Best regards, Xingyu Wu