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Date: Sat, 11 May 2024 13:18:41 +0100
From: Conor Dooley <conor@kernel.org>
To: Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v5 0/2] Add notifier for PLL0 clock and set it 1.5GHz on
Message-ID: <20240511-unbiased-dainty-ccb5ece9b1b9@spud>
References: <20240507065319.274976-1-xingyu.wu@starfivetech.com>
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On Sat, May 11, 2024 at 03:02:56AM +0000, Xingyu Wu wrote:
> On 11/05/2024 05:05, Conor Dooley wrote:
> >=20
> > On Tue, May 07, 2024 at 02:53:17PM +0800, Xingyu Wu wrote:
> > > This patch is to add the notifier for PLL0 clock and set the PLL0 rate
> > > to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.
> > >
> > > The first patch is to add the notifier for PLL0 clock. Setting the
> > > PLL0 rate need the son clock (cpu_root) to switch its parent clock to
> > > OSC clock and switch it back after setting PLL0 rate. It need to use
> > > the cpu_root clock from SYSCRG and register the notifier in the SYSCRG
> > > driver.
> > >
> > > The second patch is to set cpu_core rate to 500MHz and PLL0 rate to
> > > 1.5GHz to fix the problem about the lower rate of CPUfreq on the
> > > visionfive board. The cpu_core clock rate is set to 500MHz first to
> > > ensure that the cpu frequency will not suddenly become high and the
> > > cpu voltage is not enough to cause a crash when the PLL0 is set to 1.=
5GHz.
> > > The cpu voltage and frequency are then adjusted together by CPUfreq.
> >=20
> > Hmm, how does sequencing work here? If we split the patches between tre=
es it
> > sounds like without the dts patch, the clock tree would (or
> > could) crash, or mainline if the clock changes there before the dts one=
s do. Am I
> > misunderstanding that?
>=20
> Oh, I think you misunderstood it. Patch 1 (clock driver patch) does not c=
ause the
> clock tree crash without the patch 2 (dts patch), and it just provides th=
e correct
> flow of how to change the PLL0 rate. The patch 2 is to set the clock rate=
 of
> cpu_core and PLL0 rate, which causes the crash without patch 1. Setting c=
pu_core
> rate is to avoid crashes by insufficient cpu voltage when setting PLL0 ra=
te.

So is the problem in the other direction then? My dts tree will crash if
I apply the dts change without the clock patch?
Additionally, what about U-Boot? Will it have problems if the dts is
imported there without changes to its clock driver?

Cheers,
Conor.

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