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Date: Sat, 11 May 2024 13:52:16 +0100
From: Conor Dooley <conor@kernel.org>
To: Christian Marangi <ansuelsmth@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>,
	=?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= <zajec5@gmail.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Florian Fainelli <florian.fainelli@broadcom.com>,
	Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>,
	linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/4] dt-bindings: mips: brcm: Document
 brcm,bmips-cbr-reg property
Message-ID: <20240511-headset-self-dc2501b38a71@spud>
References: <20240509204750.1538-1-ansuelsmth@gmail.com>
 <20240509204750.1538-3-ansuelsmth@gmail.com>
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On Thu, May 09, 2024 at 10:47:46PM +0200, Christian Marangi wrote:
> Document brcm,bmips-cbr-reg property.
>=20
> Some SoC suffer from a BUG where CBR(Core Base Register)
> address might badly/never inizialized by the Bootloader or
> reaching it from co-processor registers if the system
> boots from secondary CPU results in invalid address.
>=20
> The CBR address is always the same on the SoC.
>=20
> Usage of this property is to give an address also in these broken
> configuration/bootloader.
>=20
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
>  .../devicetree/bindings/mips/brcm/soc.yaml    | 24 +++++++++++++++++++
>  1 file changed, 24 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Docum=
entation/devicetree/bindings/mips/brcm/soc.yaml
> index 975945ca2888..6b961b62aff2 100644
> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> @@ -55,6 +55,16 @@ properties:
>           under the "cpus" node.
>          $ref: /schemas/types.yaml#/definitions/uint32
> =20
> +      brcm,bmips-cbr-reg:
> +        description: Reference address of the CBR.
> +          Some SoC suffer from a BUG where CBR(Core Base Register)
> +          address might badly/never inizialized by the Bootloader or

"be badly or never initialized"

> +          reaching it from co-processor registers if the system

"reading"?

Otherwise,
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> +          boots from secondary CPU results in invalid address.
> +          The CBR address is always the same on the SoC hence it
> +          can be provided in DT to handle these broken case.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +
>      patternProperties:
>        "^cpu@[0-9]$":
>          type: object
> @@ -64,6 +74,20 @@ properties:
>      required:
>        - mips-hpt-frequency
> =20
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        enum:
> +          - brcm,bcm6358
> +          - brcm,bcm6368
> +
> +then:
> +  properties:
> +    cpus:
> +      required:
> +        - brcm,bmips-cbr-reg
> +
>  additionalProperties: true
> =20
>  examples:
> --=20
> 2.43.0
>=20

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