Received-SPF: pass (google.com: domain of linux-kernel+bounces-176927-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161;
Date: Sun, 12 May 2024 12:54:49 -0300
From: Jason Gunthorpe <jgg@nvidia.com>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
	thierry.reding@gmail.com, vdumpa@nvidia.com, jonathanh@nvidia.com,
	linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH v7 5/6] iommu/arm-smmu-v3: Add in-kernel support for
 NVIDIA Tegra241 (Grace) CMDQV
Message-ID: <ZkDmSe5XPTbMb+q2@nvidia.com>
References: <cover.1715147377.git.nicolinc@nvidia.com>
 <9cf877a464c359b44e87b375bdf2962d2670f0e2.1715147377.git.nicolinc@nvidia.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <9cf877a464c359b44e87b375bdf2962d2670f0e2.1715147377.git.nicolinc@nvidia.com>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?C7pSxQwvtZqBf23Ot6oWoL2M1yJunh1pO9WQUNuatO4H4LjKvRCMN8BHgRQx?=
 =?us-ascii?Q?wsYmMM1uD1UgI4kOOZFXvofxlB5VZ427cRq4473K319XSCDzQJh+ll4eLpgn?=
 =?us-ascii?Q?tEIUicBeLukmTQLZT8RWlS0PcFCH7HHQL8g2wD/WIY/dlsXg+mXMs8FZfaJD?=
 =?us-ascii?Q?Fpu5Ipnawpvj1S7+mrSuOLGOqrr5A+e5ne205dCbl2Vr7Ra3xolT+Xg65umD?=
 =?us-ascii?Q?NN9YKNJ6QLhIV7EG85I3VytvDMPjOjYgaCTaz4MDFsSE58GyaSiI4k4/UVGA?=
 =?us-ascii?Q?OykU0ChBQIZaHHURET2BxQjSpZCCLjZPIO7auq8r4+WWWWHvIA7Joy8HEzNI?=
 =?us-ascii?Q?5pHSGXtbb3b2pjcWRZ9ZU2nIirR0nQlfadf4QyG72MTK8zv3k/K1iLEi2bRS?=
 =?us-ascii?Q?z29S+J8kp226AObEHp+5wci8K3DWFseTKV38OiqsOxRwdc2rEYUE6Voy5Uj6?=
 =?us-ascii?Q?6hf0arMX9B4sTt5LRMtfFQ1Djl0hnKpiBLFHiHTwRVwcYr1/5Vh4q6qziuVe?=
 =?us-ascii?Q?UjxuRKtKf/A9deYsuMeAIqSLtx46oc8SjAC2hGeXEw5VpyPg1VAlu6xw5r8l?=
 =?us-ascii?Q?5LvTutkPg8NW6kTsHIq0ybB3lwe8DAXFRwCC97ynG1n5SNLfQBI17JN66hkt?=
 =?us-ascii?Q?iHyMHOH0s/qo2dvQeWvXatH+yUZfSpUmxsI7t6OWxknkdfNf+LV4Dw0EVt5W?=
 =?us-ascii?Q?ky+6FzbnewEEoM2Czs+eTKwMZV+JUDGnYb0BYt14DKcwcmTt16VqcHVPJWoX?=
 =?us-ascii?Q?IQ3pw2whVqX8IwVDN4Xj/sXxNOq7ADR+9pSY6fEs5wO9sZ7o2yvmXcR13Pd2?=
 =?us-ascii?Q?g6ZCTyY+91cW++mJR98IB8t4AkObcvOeXU74Z9sqX3cgwuq220P0h8wep8/4?=
 =?us-ascii?Q?NqjCFynNoqb8QXuwRir6W3KJyx6pY1lnpEplEi2kmjTlLqnMhYXjmhpc/N/F?=
 =?us-ascii?Q?GRdCuQpmPbcAltafsSLs72ljYeYflrPEbAuFrsD8TbJaLLKX7j5albpIdzSr?=
 =?us-ascii?Q?oQ37grnV60c9X77Fo9utvuWkKN/B0oDFlWdNj6LAtyGkjsK159r54JoHhnTL?=
 =?us-ascii?Q?Wf1nRCGCvFvTw7gUUCONxdsk6f9npA/ucczT8nRMq3qkk4tUgyRVsJ7EzaOI?=
 =?us-ascii?Q?Crbv+/5k66u7LwZ2WhzSpzmFiVQIkHiSV3gq8WMBdNROa3TiX9TAPqw1MV/l?=
 =?us-ascii?Q?lIUOxz+tAH/hEQNlsZvtT74p69zbIwtSHQlN8zFLJYvqnCD59Hj6YIKbviuo?=
 =?us-ascii?Q?iQKxCyJfX9rqRZdgg+kF8i4eccVsa8z1bcGDihxEiDewXekgfA/0K/v3WisP?=
 =?us-ascii?Q?imO0BjsKIUx46IVRq/6rRusbx/RI/NPzwNPA01HYxmFFRihN1sa2/lnVdNdq?=
 =?us-ascii?Q?lJ4gNjo3NfDxzg6fMS45Rz/0+K8jxPgc1C4epgdFG3EhJ5r4GWgy6UzJDRef?=
 =?us-ascii?Q?AS8DcagZ3PtcjRmU43StieLYIuocdoymC1LDrd+WwJmzobpjyyzoN8oNTNRa?=
 =?us-ascii?Q?49mBvdyRhCfG/NFnLWsaDuOvCn5j6dzodhR06p4Xepu2fjagaf+A/OZIzWnu?=
 =?us-ascii?Q?eYM7AYdQtzNVaMOgxCpLqHpITHW7V6TrSqds1G0a?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 48f37406-50a5-4ace-d3bc-08dc729be05d
X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3849.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2024 15:54:59.0667
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: cSsziKbiFLB8hTmy73fTIPzkWGlO7ukPXsJYSN0CAlhpwfUrBLvR1/f+xmMA6ugG
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5859

On Tue, May 07, 2024 at 10:56:53PM -0700, Nicolin Chen wrote:

> +/* MMIO helpers */
> +#define cmdqv_readl(_cmdqv, _regname) \
> +	readl((_cmdqv)->base + TEGRA241_CMDQV_##_regname)
> +#define cmdqv_readl_relaxed(_cmdqv, _regname) \
> +	readl_relaxed((_cmdqv)->base + TEGRA241_CMDQV_##_regname)
> +#define cmdqv_readq_relaxed(_cmdqv, _regname) \
> +	readq_relaxed((_cmdqv)->base + TEGRA241_CMDQV_##_regname)
> +#define cmdqv_writel(_cmdqv, val, _regname) \
> +	writel((val), (_cmdqv)->base + TEGRA241_CMDQV_##_regname)
> +#define cmdqv_writel_relaxed(_cmdqv, val, _regname) \
> +	writel_relaxed((val), (_cmdqv)->base + TEGRA241_CMDQV_##_regname)
> +
> +#define vintf_readl(_vintf, _regname) \
> +	readl((_vintf)->base + TEGRA241_VINTF_##_regname)
> +#define vintf_readq_relaxed(_vintf, _regname) \
> +	readq_relaxed((_vintf)->base + TEGRA241_VINTF_##_regname)
> +#define vintf_readl_relaxed(_vintf, _regname) \
> +	readl_relaxed((_vintf)->base + TEGRA241_VINTF_##_regname)
> +#define vintf_writel(_vintf, val, _regname) \
> +	writel((val), (_vintf)->base + TEGRA241_VINTF_##_regname)
> +#define vintf_writel_relaxed(_vintf, val, _regname) \
> +	writel_relaxed((val), (_vintf)->base + TEGRA241_VINTF_##_regname)
> +
> +#define vcmdq_page0_readl(_vcmdq, _regname) \
> +	readl((_vcmdq)->page0 + TEGRA241_VCMDQ_##_regname)
> +#define vcmdq_page0_readl_relaxed(_vcmdq, _regname) \
> +	readl_relaxed((_vcmdq)->page0 + TEGRA241_VCMDQ_##_regname)
> +#define vcmdq_page0_writel(_vcmdq, val, _regname) \
> +	writel((val), (_vcmdq)->page0 + TEGRA241_VCMDQ_##_regname)
> +#define vcmdq_page0_writel_relaxed(_vcmdq, val, _regname) \
> +	writel_relaxed((val), (_vcmdq)->page0 + TEGRA241_VCMDQ_##_regname)
> +
> +#define vcmdq_page1_readl(_vcmdq, reg) \
> +	readl((_vcmdq)->page1 + TEGRA241_VCMDQ_##reg)
> +#define vcmdq_page1_readl_relaxed(_vcmdq, reg) \
> +	readl_relaxed((_vcmdq)->page1 + TEGRA241_VCMDQ_##reg)
> +#define vcmdq_page1_readq_relaxed(_vcmdq, reg) \
> +	readq_relaxed((_vcmdq)->page1 + TEGRA241_VCMDQ_##reg)
> +#define vcmdq_page1_writel(_vcmdq, val, reg) \
> +	writel((val), (_vcmdq)->page1 + TEGRA241_VCMDQ_##reg)
> +#define vcmdq_page1_writel_relaxed(_vcmdq, val, reg) \
> +	writel_relaxed((val), (_vcmdq)->page1 + TEGRA241_VCMDQ_##reg)
> +#define vcmdq_page1_writeq(_vcmdq, val, reg) \
> +	writeq((val), (_vcmdq)->page1 + TEGRA241_VCMDQ_##reg)
> +#define vcmdq_page1_writeq_relaxed(_vcmdq, val, reg) \
> +	writeq_relaxed((val), (_vcmdq)->page1 + TEGRA241_VCMDQ_##reg)

These still need to be trimmed to only the ones being used. I still
think it is a bad idea, maybe a middle ground is to wrapper the
regsiter coding

writeq_relaxed(val, REG_CMDQ_PAGE1(vcmdq, XXX));

Is still short enough and safe enough without creating so much obfuscation..

I didn't notice anything else in this patch

Jason