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Sun, 12 May 2024 13:56:42 -0700 Date: Sun, 12 May 2024 13:56:40 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , , , , , , , , , Subject: Re: [PATCH v7 3/6] iommu/arm-smmu-v3: Enforce arm_smmu_cmdq_build_sync_cmd Message-ID: References: <52845c9fdfdd7f38a694e7727f3eabbd10e9f8ee.1715147377.git.nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026368:EE_|SA1PR12MB6702:EE_ X-MS-Office365-Filtering-Correlation-Id: 639649b3-89eb-40e8-8e60-08dc72c60912 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|82310400017|1800799015; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gSi1sr1Sl2nEt//zZz6oCmfelJOquZ03P3mQg4AXNG2djIypYN9kcvfIx8rz?= =?us-ascii?Q?Uzzf3KFIyps6f+qs5GZ/2Z/aBINzv271xSEMpxDNDVpcni0lweJKeeKhPiDL?= =?us-ascii?Q?i18LivZErkcYauk5YTs8yWaQsI60p90DQ4oooWhtuasGJ9IOHyw/XawEtcaK?= =?us-ascii?Q?OujIr2yYRdwi5AW7q0ZZcK/+PNN9AakLPPCFB6JD0B4CvLc6u8yD2PgUfd7j?= =?us-ascii?Q?55ZhlhPWqMA+J8Oez3cprXyz8N7QCrOkhXUJ2dUpD/UOxfA9pvdo5Q/dMM6j?= =?us-ascii?Q?GdpsZEzbFbYR9ITkpu7Gc1qT96oeDN42nsLJVieA3Dbu46d8tOHG8b85fimb?= =?us-ascii?Q?KcVlmEf2/hEE/ShTTV/7nLxIza7ZbyaaFNDHhrNQSgR9Kyt/t5btqkTA1CYv?= =?us-ascii?Q?sX3vIuTTgrPBKqJXxizlj4Rzv8ifwnQhzbYEVCTUdEWh9zeXdd1Xe+isvGd3?= =?us-ascii?Q?Oqp0SDvZcFMS6goi92mU1W4XqrWVY7+wPqT+LZZqw3XxqgG8nPl+MBKc78Zy?= =?us-ascii?Q?UcSj4Y24WNn35wyYDtBz5jE9pd3LLEt2Sep1O36jGygLtYpib6bN0MBQ13Nz?= =?us-ascii?Q?TLbgT71VT2/J+IsJa1ogs+EeDDc3PM7cwgnsBILzFviGTC6gx07eij9d22dB?= =?us-ascii?Q?tKGh+7hwlWT77axVL1zaMKVqTXI5N5ChSa5V5/zg78lLHLUDc1P2Asgl2K/S?= =?us-ascii?Q?5NTyTjnvI7taEtE+V1Z9i0rXMFOQK0g+AwgGoW7lwjOFto6Ye2QLQk6qSxEV?= =?us-ascii?Q?0634clmrVey0J8GImer8zNhj8Ts/M64lhw2gfUt1aZutN042+kwshOTa153S?= =?us-ascii?Q?D3ccaN/uo2QZZ/cOlyxIqF3iDctPX5PWOX8fOJWsgumfSCFNsoNNiYmAzeI/?= =?us-ascii?Q?MOqg3MfYPFJpF/Kx3IpLgHmWS/6UfrBYTkLJeHfldIcJcvCzFl7nbmX9Te8F?= =?us-ascii?Q?WdDJ9YiiQwQDechH/YyMZtKJzm9HrRJjLXYpZMDJoQs2l3mx8SCrLokdTL5Q?= =?us-ascii?Q?7t8hjVoM0T3sFY6KzNPmGmzdBuGzrn3cEG+FVJTUl3z8Qk7xscRvNc8uBdDd?= =?us-ascii?Q?OhN5mBs0Xo31Ucb9l+ECBx0gWNww2Uxq1qMO+a7OgeHCYGpPX6wsY78qd4PZ?= =?us-ascii?Q?DMQuxq10dt4HhUWy70w9dsG00XGax6zYhVxxJ4uTdCe3UqsVctgJMXboiJz6?= =?us-ascii?Q?d5iw+BOvUbSCcUSe4k+gj0sXAAvUeJ7UmKkQD2kuXwR2UVkXABWA4CgZc7LS?= =?us-ascii?Q?cIB6x495XkE7MaKu5laKPIEeyXDY9z906kIFse8nc/eOhU23VnjDpRO2SC/Z?= =?us-ascii?Q?EHPi6YoxX84Gm5JUn2TJK3stWzFnxZ7fZV8F+5YPQdbEhMINJxKRYLHI39aR?= =?us-ascii?Q?gO6pD1kyMwhIsw9nvWLg5HUdrU6f?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(36860700004)(82310400017)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2024 20:56:45.9663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 639649b3-89eb-40e8-8e60-08dc72c60912 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026368.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6702 On Sun, May 12, 2024 at 12:39:43PM -0300, Jason Gunthorpe wrote: > On Tue, May 07, 2024 at 10:56:51PM -0700, Nicolin Chen wrote: > > There is an existing arm_smmu_cmdq_build_sync_cmd() so the driver should > > call it at all places other than going through arm_smmu_cmdq_build_cmd() > > separately. This helps the following patch that adds a CS_NONE quirk for > > tegra241-cmdqv driver. > > > > Note that this changes the type of CMD_SYNC in __arm_smmu_cmdq_skip_err, > > for ARM_SMMU_OPT_MSIPOLL=true cases, from previously a non-MSI one to an > > MSI one that is proven to still work by a hacking test: > > nvme: Adding to iommu group 10 > > nvme: --------hacking----------- > > arm-smmu-v3: unexpected global error reported (0x00000001), > > this could be serious > > arm-smmu-v3: CMDQ error (cons 0x01000022): Illegal command > > arm-smmu-v3: skipping command in error state: > > arm-smmu-v3: 0x0000000000000000 > > arm-smmu-v3: 0x0000000000000000 > > nvme: -------recovered---------- > > nvme nvme0: 72/0/0 default/read/poll queues > > nvme0n1: p1 p2 > > Nice > > > @@ -350,20 +340,23 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) > > static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, > > struct arm_smmu_queue *q, u32 prod) > > { > > - struct arm_smmu_cmdq_ent ent = { > > - .opcode = CMDQ_OP_CMD_SYNC, > > - }; > > + memset(cmd, 0, 1 << CMDQ_ENT_SZ_SHIFT); > > The command would also benifit from its own type someday :\ > > Maybe this should just be cmd[1] = 0 ? Yes. I will add that. > Reviewed-by: Jason Gunthorpe Thanks! Nicolin