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Sun, 12 May 2024 14:01:02 -0700 Date: Sun, 12 May 2024 14:00:59 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , , , , , , , , , Subject: Re: [PATCH v7 5/6] iommu/arm-smmu-v3: Add in-kernel support for NVIDIA Tegra241 (Grace) CMDQV Message-ID: References: <9cf877a464c359b44e87b375bdf2962d2670f0e2.1715147377.git.nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D1:EE_|SJ2PR12MB7944:EE_ X-MS-Office365-Filtering-Correlation-Id: d225ea60-cb5c-4b09-fb02-08dc72c6ac63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|1800799015|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KjsME56UGY75jwfFRj7t0xATantJt4RMIqOECklzkm+Yy9BVxjf14yYY9bu6?= =?us-ascii?Q?RwNx+FTTxmPZuEtovg+9qFxpkJwA7pDir7Z5RSN2s/TOEWiRjMLbwga1YkUy?= =?us-ascii?Q?d6ypPbLzLimnvSyj4vCF+7WaqbKtAFBp8SMLAGYIhmOVUS5O4I4Sn3GwWSOX?= =?us-ascii?Q?O96jAkuXUtVNPLgwYZ4Jcgofj3rOF1H75eppP0oDw9Dz5stsPwWqRAfCYrxi?= =?us-ascii?Q?MCmDUEBrozXZzT4tuk7a51hS40tosGxKy5+bRnUwCdI67yP3H6SJWef/Vql9?= =?us-ascii?Q?h01kznOKU0Xj5mhnsxqUMtezFtl0XhbV7SFtwR18y9o4XYV0fbNciMTRNzq9?= =?us-ascii?Q?BvYhzsx5IjJ6s50kgGvRmcRum+YswvCwwb7/pg7RiFxl157Nj6NssQW0Vj3/?= =?us-ascii?Q?s+Ah1Y8/sPBSjVeWteRtiXeD5XijoExiVXojPVIOzE1XJ8xecKbDUCuUm9o+?= =?us-ascii?Q?l9ASwzw4M239MfupMYuOBDad8Gy4B7zp7GY8wRL9DGbDhl02dBjjdoBII0TH?= =?us-ascii?Q?/FpR3cSWh8tv9d14JeiAwduyikVUolo8cHPsaePybNrYi2gc3q3Uzyr8CcqQ?= =?us-ascii?Q?rGSQwB4owqK018i3UM6+5zRzQibPYNyRGe+YmadK/UEXAyqHvNlG839tS5q2?= =?us-ascii?Q?BLhXAMUwHc+69xYnvG83tmXNVt+OKSH4vc2PVWs/VpxqhPXWncAyM4XTzbBX?= =?us-ascii?Q?KYgSqMfTVWevt9+ogJZG+FYst5CxYj800n27QV92HO8EdF1d24NHLYAFndnl?= =?us-ascii?Q?vGt4iDCmXWIXYEK7bI4R5ZRo0oveJ1p4XJ2RvSwKywROt7pA2cgjVyNBFfEe?= =?us-ascii?Q?TzlnJ2udakADWZPtsH25i+557qQpDXYDVF7P3dN0i8mpJBYanJJtQOaeNXkK?= =?us-ascii?Q?GgxDPcx6KQH3pVM9kNsZduMqTozT3dzKqLlgdgvFfj3aLuvsMD9WsapLjYPL?= =?us-ascii?Q?jcCB2R3OvN8qSknEWf0vBb529LIq+Hotq1efRMS/IFgs64PBNI4YlIWHLUrm?= =?us-ascii?Q?BdzUi6+hMYPdvEGm4gQZY+2msj+Hl22BCWxh/tzE58XQEdszsOEfNQTxb3Kn?= =?us-ascii?Q?YEN5BXZgKTs+Aq9iOUmS6Kd/zF7ntBCcONQynK51+MfaPJAEroM9TOQltQqu?= =?us-ascii?Q?B4Nycepl6p/pgrQjCZRo0QStDRdq2/GsncREKOanhFXx1KHymOpemHgxadoe?= =?us-ascii?Q?jDXHWHmIcU0YPcszmmrbhsyes9jNInmjdbmFYujXspxt8AMgdhMkxHpV+OON?= =?us-ascii?Q?yH6cJIeQKTDF0/GixPspFRuzQsSSuX1B7yZCyQ4uc5lqJot3smamSW6PjXoU?= =?us-ascii?Q?XSO54lb6EfAjv/2jFT1uUe2F7MRoXlcuIOGWWjHQeFb3TKDLlQgE9bBn04MT?= =?us-ascii?Q?fqN3laY=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(1800799015)(36860700004)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2024 21:01:20.0779 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d225ea60-cb5c-4b09-fb02-08dc72c6ac63 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7944 On Sun, May 12, 2024 at 12:54:49PM -0300, Jason Gunthorpe wrote: > On Tue, May 07, 2024 at 10:56:53PM -0700, Nicolin Chen wrote: > > +#define vcmdq_page1_readl(_vcmdq, reg) \ > > + readl((_vcmdq)->page1 + TEGRA241_VCMDQ_##reg) > > +#define vcmdq_page1_readl_relaxed(_vcmdq, reg) \ > > + readl_relaxed((_vcmdq)->page1 + TEGRA241_VCMDQ_##reg) > > +#define vcmdq_page1_readq_relaxed(_vcmdq, reg) \ > > + readq_relaxed((_vcmdq)->page1 + TEGRA241_VCMDQ_##reg) > > +#define vcmdq_page1_writel(_vcmdq, val, reg) \ > > + writel((val), (_vcmdq)->page1 + TEGRA241_VCMDQ_##reg) > > +#define vcmdq_page1_writel_relaxed(_vcmdq, val, reg) \ > > + writel_relaxed((val), (_vcmdq)->page1 + TEGRA241_VCMDQ_##reg) > > +#define vcmdq_page1_writeq(_vcmdq, val, reg) \ > > + writeq((val), (_vcmdq)->page1 + TEGRA241_VCMDQ_##reg) > > +#define vcmdq_page1_writeq_relaxed(_vcmdq, val, reg) \ > > + writeq_relaxed((val), (_vcmdq)->page1 + TEGRA241_VCMDQ_##reg) > > These still need to be trimmed to only the ones being used. I still > think it is a bad idea, maybe a middle ground is to wrapper the > regsiter coding > > writeq_relaxed(val, REG_CMDQ_PAGE1(vcmdq, XXX)); > > Is still short enough and safe enough without creating so much obfuscation.. I think that is a much better practice! Let me try with it. Thanks! Nicolin