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[147.75.199.223]) by mx.google.com with ESMTPS id af79cd13be357-792bf277e45si863943285a.66.2024.05.12.22.29.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 May 2024 22:29:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-177165-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of linux-kernel+bounces-177165-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-177165-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 4739C1C20F13 for ; Mon, 13 May 2024 05:29:03 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 37161146583; Mon, 13 May 2024 05:28:57 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 42CA0146006 for ; Mon, 13 May 2024 05:28:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715578136; cv=none; b=AXsce7wfadxhu+cTCqXZz0FVKlEyfto3zcPkV04WlZknCMQXLvFvrqcEqhz8fJvvZ7PxK/WTPi53fDktRcB0EDpZLxIdEsYbZtUn9qrScFoAX7g/4vCXUHEAn8M8/wthTrW+0vTSRReHsIvdsvIJL+9HrcXz0SSQHMAnSLIe75Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715578136; c=relaxed/simple; bh=VLqQIw9DxsfdiVNjqe2D3rzPWsmGB7eOKlY0suFaJa4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=cnBxROaW+hy73dLbNW3+RNM0NpaTFUDoLvGPX1f0se2t+tBm87Z1Pjsh604abddqbBz0dQRtqGanN3l+xLipXP+X/gXTZ48YiU+yMKRpiDPbI9a8MKEw5IeMLfdTh+G+3ltx2Z5VwVcjXQ4QX+2HYHrD66KbjTbj2IwFEELcfnU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA4871007; Sun, 12 May 2024 22:29:13 -0700 (PDT) Received: from [10.163.38.21] (unknown [10.163.38.21]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 254D13F762; Sun, 12 May 2024 22:28:44 -0700 (PDT) Message-ID: Date: Mon, 13 May 2024 10:58:53 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] KVM: arm64: Replace custom macros with fields from ID_AA64PFR0_EL1 Content-Language: en-US To: Mark Rutland Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, Oliver Upton , Will Deacon , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, Fuad Tabba References: <20240418053804.2573071-1-anshuman.khandual@arm.com> <20240418053804.2573071-2-anshuman.khandual@arm.com> <871q73rufi.wl-maz@kernel.org> From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/10/24 23:39, Mark Rutland wrote: > On Mon, Apr 29, 2024 at 07:53:14AM +0530, Anshuman Khandual wrote: >> On 4/18/24 13:09, Marc Zyngier wrote: >>> On Thu, 18 Apr 2024 06:38:03 +0100, >>> Anshuman Khandual wrote: >>>> #define PVM_ID_AA64PFR0_RESTRICT_UNSIGNED (\ >>>> - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ >>>> - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ >>>> - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ >>>> - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ >>>> + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_EL0_IMP) | \ >>>> + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_EL1_IMP) | \ >>>> + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_EL2_IMP) | \ >>>> + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_EL3_IMP) | \ >>> >>> If you are going to rework this, can we instead use something less >>> verbose such as SYS_FIELD_GET()? >> >> Just wondering, is not FIELD_PREP() and SYS_FIELD_GET() does the exact opposite thing. >> The earlier builds the entire register value from various constituents, where as the >> later extracts a single register field from a complete register value instead. Or did >> I just misunderstood something here. > > He means use one of the SYS_FIELD_*() helpers, e.g. SYS_FIELD_PREP_ENUM(), with > which this can be: > > #define PVM_ID_AA64PFR0_RESTRICT_UNSIGNED (\ > SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL0, IMP) | \ > SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL1, IMP) | \ > SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL2, IMP) | \ > SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL3, IMP) | \ > SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, RAS, IMP) \ > ) > > ... which is far less verbose, and much easier to read. Got it, this makes sense, will fold in the above changes and respin after the merge window. Thanks for the clarification.