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References: <20240510-imx-clk-v2-0-c998f315d29c@nxp.com> <20240510-imx-clk-v2-5-c998f315d29c@nxp.com>
In-Reply-To: <20240510-imx-clk-v2-5-c998f315d29c@nxp.com>
From: Adam Ford <aford173@gmail.com>
Date: Mon, 13 May 2024 07:40:34 -0500
Message-ID: <CAHCN7xKXjuEBb1wTm0-r-j4iCnSYuq_f-AtPpOZG-h7DtSo4aQ@mail.gmail.com>
Subject: Re: [PATCH v2 05/17] clk: imx: pll14xx: Add constraint for fvco frequency
To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc: Abel Vesa <abelvesa@kernel.org>, Michael Turquette <mturquette@baylibre.com>, 
	Stephen Boyd <sboyd@kernel.org>, Shawn Guo <shawnguo@kernel.org>, 
	Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, 
	Fabio Estevam <festevam@gmail.com>, Jacky Bai <ping.bai@nxp.com>, Ye Li <ye.li@nxp.com>, 
	Dong Aisheng <aisheng.dong@nxp.com>, linux-clk@vger.kernel.org, imx@lists.linux.dev, 
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 
	Abel Vesa <abel.vesa@linaro.org>, Peng Fan <peng.fan@nxp.com>, 
	Shengjiu Wang <shengjiu.wang@nxp.com>, Chancel Liu <chancel.liu@nxp.com>
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On Fri, May 10, 2024 at 4:14=E2=80=AFAM Peng Fan (OSS) <peng.fan@oss.nxp.co=
m> wrote:
>
> From: Shengjiu Wang <shengjiu.wang@nxp.com>
>
> The fvco frequency range is between 1600MHz and 3200MHz, without
> this constraint the fvco may out of range, the real output
> frequency is no accurate.
>
> Aslo correct the name for fvco and fout clock.
>
> Fixes: b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates")
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> Acked-by: Jacky Bai <ping.bai@nxp.com>
> Tested-by: Chancel Liu <chancel.liu@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk-pll14xx.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.=
c
> index d63564dbb12c..55812bfb9ec2 100644
> --- a/drivers/clk/imx/clk-pll14xx.c
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -131,7 +131,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll1=
4xx *pll, unsigned long rat
>  {
>         u32 pll_div_ctl0, pll_div_ctl1;
>         int mdiv, pdiv, sdiv, kdiv;
> -       long fout, rate_min, rate_max, dist, best =3D LONG_MAX;
> +       long fvco, fout, rate_min, rate_max, dist, best =3D LONG_MAX;
>         const struct imx_pll14xx_rate_table *tt;
>
>         /*
> @@ -144,6 +144,8 @@ static void imx_pll14xx_calc_settings(struct clk_pll1=
4xx *pll, unsigned long rat
>          *
>          * fvco =3D (m * 65536 + k) * prate / (p * 65536)
>          * fout =3D (m * 65536 + k) * prate / (p * 65536) / (1 << sdiv)
> +        *
> +        * e) 1600MHz <=3D fvco <=3D 3200MHz
>          */
>
>         /* First try if we can get the desired rate from one of the stati=
c entries */
> @@ -193,6 +195,10 @@ static void imx_pll14xx_calc_settings(struct clk_pll=
14xx *pll, unsigned long rat
>                         kdiv =3D pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rat=
e, prate);
>                         fout =3D pll14xx_calc_rate(pll, mdiv, pdiv, sdiv,=
 kdiv, prate);
>
> +                       fvco =3D fout << sdiv;

The calculation of fvco here does not match the comment above where
fvco =3D (m * 65536 + k) * prate / (p * 65536)


> +
> +                       if (fvco < 1600000000 || fvco > 3200000000)
> +                               continue;
>                         /* best match */
>                         dist =3D abs((long)rate - (long)fout);
>                         if (dist < best) {
>
> --
> 2.37.1
>
>