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Mon, 13 May 2024 10:45:06 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCXe4xHUGkukGKLY+rW39OK6N1anGVy617lKxvzOsfHo+Ng8gJqoqie4VKwF8RWspwpDCrHU16jUe3rFXN5LJ/pipKrdeuTd87f8vWmZ X-Gm-Message-State: AOJu0YxrzlkVlH2VimOJ4c0nXDMbrWLTMZKVNJNEuTPGsuNLcxJgrzOm UjFHe7VPaBi3tlfItknGsESlfsTQ/GxzBJxX8m46LPEUcTvm8xswW5+9Ueglc05BMUj3p+Ty/rM N/YarQrrpuY0GIi+6p9qz4KuqS5HOgzDTiMqsxg== X-Received: by 2002:a25:bc8f:0:b0:dee:6346:b856 with SMTP id 3f1490d57ef6-dee6346bbaemr6453224276.34.1715622305916; Mon, 13 May 2024 10:45:05 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240506094644.887842-1-kuro.chung@ite.com.tw> <20240506094644.887842-2-kuro.chung@ite.com.tw> In-Reply-To: From: Robert Foss Date: Mon, 13 May 2024 19:44:55 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v7 1/1] drm/bridge: it6505: fix hibernate to resume no display issue To: kuro Cc: Allen Chen , Pin-yen Lin , Kenneth Haung , Kuro Chung , Andrzej Hajda , Neil Armstrong , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , "open list:DRM DRIVERS" , open list Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, May 13, 2024 at 7:42=E2=80=AFPM Robert Foss wrot= e: > > On Mon, May 6, 2024 at 11:36=E2=80=AFAM kuro wrot= e: > > > > From: Kuro > > > > ITE added a FIFO reset bit for input video. When system power resume, > > the TTL input of it6505 may get some noise before video signal stable > > and the hardware function reset is required. > > But the input FIFO reset will also trigger error interrupts of output m= odule rising. > > Thus, it6505 have to wait a period can clear those expected error inter= rupts > > caused by manual hardware reset in one interrupt handler calling to avo= id interrupt looping. > > > > Signed-off-by: Kuro Chung > > > > --- > > drivers/gpu/drm/bridge/ite-it6505.c | 73 +++++++++++++++++++---------- > > 1 file changed, 49 insertions(+), 24 deletions(-) > > > > diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/brid= ge/ite-it6505.c > > index b53da9bb65a16..64e2706e3d0c3 100644 > > --- a/drivers/gpu/drm/bridge/ite-it6505.c > > +++ b/drivers/gpu/drm/bridge/ite-it6505.c > > @@ -1317,9 +1317,15 @@ static void it6505_video_reset(struct it6505 *it= 6505) > > it6505_link_reset_step_train(it6505); > > it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID= _MUTE); > > it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x= 00); > > - it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESE= T); > > + > > + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, TX_FI= FO_RESET); > > + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x00)= ; > > + > > it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_50= 1_FIFO); > > it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00); > > + > > + it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESE= T); > > + usleep_range(1000, 2000); > > it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00); > > } > > > > @@ -2249,12 +2255,11 @@ static void it6505_link_training_work(struct wo= rk_struct *work) > > if (ret) { > > it6505->auto_train_retry =3D AUTO_TRAIN_RETRY; > > it6505_link_train_ok(it6505); > > - return; > > } else { > > it6505->auto_train_retry--; > > + it6505_dump(it6505); > > } > > > > - it6505_dump(it6505); > > } > > > > static void it6505_plugged_status_to_codec(struct it6505 *it6505) > > @@ -2475,31 +2480,53 @@ static void it6505_irq_link_train_fail(struct i= t6505 *it6505) > > schedule_work(&it6505->link_works); > > } > > > > -static void it6505_irq_video_fifo_error(struct it6505 *it6505) > > +static bool it6505_test_bit(unsigned int bit, const unsigned int *addr= ) > > { > > - struct device *dev =3D &it6505->client->dev; > > - > > - DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt"); > > - it6505->auto_train_retry =3D AUTO_TRAIN_RETRY; > > - flush_work(&it6505->link_works); > > - it6505_stop_hdcp(it6505); > > - it6505_video_reset(it6505); > > + return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE))= ; > > } > > > > -static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505) > > +static void it6505_irq_video_handler(struct it6505 *it6505, const int = *int_status) > > { > > struct device *dev =3D &it6505->client->dev; > > + int reg_0d, reg_int03; > > > > - DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt"); > > - it6505->auto_train_retry =3D AUTO_TRAIN_RETRY; > > - flush_work(&it6505->link_works); > > - it6505_stop_hdcp(it6505); > > - it6505_video_reset(it6505); > > -} > > + /* > > + * When video SCDT change with video not stable, > > + * Or video FIFO error, need video reset > > + */ > > > > -static bool it6505_test_bit(unsigned int bit, const unsigned int *addr= ) > > -{ > > - return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE))= ; > > + if ((!it6505_get_video_status(it6505) && > > + (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *) int_= status))) || > > + (it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW, (unsigned in= t *) int_status)) || > > + (it6505_test_bit(BIT_INT_VID_FIFO_ERROR, (unsigned int = *) int_status))) { > > + > > + it6505->auto_train_retry =3D AUTO_TRAIN_RETRY; > > + flush_work(&it6505->link_works); > > + it6505_stop_hdcp(it6505); > > + it6505_video_reset(it6505); > > + > > + usleep_range(10000, 11000); > > + > > + /* > > + * Clear FIFO error IRQ to prevent fifo error -> reset = loop > > + * HW will trigger SCDT change IRQ again when video sta= ble > > + */ > > + > > + reg_int03 =3D it6505_read(it6505, INT_STATUS_03); > > + reg_0d =3D it6505_read(it6505, REG_SYSTEM_STS); > > + > > + reg_int03 &=3D (BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LA= TCH_FIFO_OVERFLOW)); > > + it6505_write(it6505, INT_STATUS_03, reg_int03); > > + > > + DRM_DEV_DEBUG_DRIVER(dev, "reg08 =3D 0x%02x", reg_int03= ); > > + DRM_DEV_DEBUG_DRIVER(dev, "reg0D =3D 0x%02x", reg_0d); > > + > > + return; > > + } > > + > > + > > + if (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *) int_statu= s)) > > + it6505_irq_scdt(it6505); > > } > > > > static irqreturn_t it6505_int_threaded_handler(int unused, void *data) > > @@ -2512,15 +2539,12 @@ static irqreturn_t it6505_int_threaded_handler(= int unused, void *data) > > } irq_vec[] =3D { > > { BIT_INT_HPD, it6505_irq_hpd }, > > { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq }, > > - { BIT_INT_SCDT, it6505_irq_scdt }, > > { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail }, > > { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done }, > > { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail }, > > { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check }, > > { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error= }, > > { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail }= , > > - { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error }= , > > - { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_ov= erflow }, > > }; > > int int_status[3], i; > > > > @@ -2550,6 +2574,7 @@ static irqreturn_t it6505_int_threaded_handler(in= t unused, void *data) > > if (it6505_test_bit(irq_vec[i].bit, (unsigned i= nt *)int_status)) > > irq_vec[i].handler(it6505); > > } > > + it6505_irq_video_handler(it6505, (unsigned int *) int_s= tatus); > > } > > > > pm_runtime_put_sync(dev); > > -- > > 2.25.1 > > > > Reviewed-by: Robert Foss This patch does not apply on drm-misc-next, please fix this and then this patch is ready to be applied.