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Date: Mon, 13 May 2024 21:52:32 +0200
From: Andrew Lunn <andrew@lunn.ch>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>,
	netdev@vger.kernel.org, davem@davemloft.net, edumazet@google.com,
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	linux-arm-kernel@lists.infradead.org,
	Herve Codina <herve.codina@bootlin.com>
Subject: Re: [PATCH v2, net-next, 2/2] net: stmmac: PCI driver for BCM8958X
 SoC
Message-ID: <ea0485f6-fc7d-4e02-884c-05d77420d6ea@lunn.ch>
References: <20240510000331.154486-3-jitendra.vegiraju@broadcom.com>
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 <Zj/IPpub11OL3jBo@shell.armlinux.org.uk>
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On Mon, May 13, 2024 at 06:41:35PM +0100, Russell King (Oracle) wrote:
> On Mon, May 13, 2024 at 10:38:46AM -0700, Jitendra Vegiraju wrote:
> > Thanks for reviewing the patch.
> > On Sat, May 11, 2024 at 12:34 PM Russell King (Oracle)
> > <linux@armlinux.org.uk> wrote:
> > > As pointed out in the other sub-thread, you don't need this. If you need
> > > a fixed-link and you don't have a firmware description of it, you can
> > > provide a swnode based description through plat->port_node that will be
> > > passed to phylink. Through that, you can tell phylink to create a
> > > fixed link.
> > >
> > Thank you for the pointers or software node support.
> > Since the driver is initially targetted for X86/_64, we were not sure
> > how to deal with lack of OF support.
> > We will try out the software node facility.
> 
> You may wish to have a look at drivers/net/ethernet/wangxun/ which
> also creates software nodes for phylink.

How complex is the switch configuration? So far, you have not said
anything about it. Is it derived from b53/SF2?

There is an alternative route you can take. Work with bootlin and use
DT overlays.

https://lore.kernel.org/linux-pci/20240430083730.134918-1-herve.codina@bootlin.com/

Looking at the product brief, the BCM89586M has MDIO busses, SPI
busses, GPIO, etc. It is unclear if these are available on the PCIe
interface, or are only connected to the Cortex-M7? I would guess the
QSPI, DEBUG/JTAG and the UART go to the M7, for its boot media and
console. But the other interfaces could be for Linux to control over
the PCIe. Additionally, the PHY-less ports doing XFI, 5G, 2.5G SGMII
etc, would have either an SFP or multi-gigi PHY connected, hanging of
one of the MDIO busses, GPIOs used for SFP LOS, TX-enable etc. Oddly
there is no I2C for the SPF, but i suppose you could do SPI->I2C.
Anyway, all that is going to need a complex configuration, so maybe DT
overlays make sense, because once the initial work getting Bootlins
patches merged is complete, you get the rest pretty much for free.

	Andrew