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Date: Tue, 14 May 2024 18:57:04 +0100
From: Conor Dooley <conor@kernel.org>
To: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	valentina.fernandezalanis@microchip.com
Subject: Re: [PATCH v2 3/3] spi: spi-microchip-core: Add support for GPIO
 based CS
Message-ID: <20240514-malt-diffuser-2fd207015e72@spud>
References: <20240514104508.938448-1-prajna.rajendrakumar@microchip.com>
 <20240514104508.938448-4-prajna.rajendrakumar@microchip.com>
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Prajna, Mark,

On Tue, May 14, 2024 at 11:45:08AM +0100, Prajna Rajendra Kumar wrote:
> The SPI "hard" controller within the PolarFire SoC is capable of
> handling eight CS lines, but only one CS line is wired. Therefore, use
> GPIO descriptors to configure additional CS lines.
>=20
> Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>

I provided an ack on v1, so here it is again:
Acked-by: Conor Dooley <conor.dooley@microchip.com>

In general you can keep tags between versions, if you intentionally drop
tags you should mention why you dropped them.

> ---
>  drivers/spi/spi-microchip-core.c | 4 ++++
>  1 file changed, 4 insertions(+)
>=20
> diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip=
-core.c
> index c10de45aa472..6246254e1dff 100644
> --- a/drivers/spi/spi-microchip-core.c
> +++ b/drivers/spi/spi-microchip-core.c
> @@ -258,6 +258,9 @@ static int mchp_corespi_setup(struct spi_device *spi)
>  	struct mchp_corespi *corespi =3D spi_controller_get_devdata(spi->contro=
ller);
>  	u32 reg;
> =20
> +	if (spi_is_csgpiod(spi))
> +		return 0;

Mark,

This has no users outside of core code, but is < 6 months old. Is using
it in a driver like this okay?

Cheers,
Conor.

> +
>  	/*
>  	 * Active high targets need to be specifically set to their inactive
>  	 * states during probe by adding them to the "control group" & thus
> @@ -516,6 +519,7 @@ static int mchp_corespi_probe(struct platform_device =
*pdev)
> =20
>  	host->num_chipselect =3D num_cs;
>  	host->mode_bits =3D SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
> +	host->use_gpio_descriptors =3D true;
>  	host->setup =3D mchp_corespi_setup;
>  	host->bits_per_word_mask =3D SPI_BPW_MASK(8);
>  	host->transfer_one =3D mchp_corespi_transfer_one;
> --=20
> 2.25.1
>=20
>=20
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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