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Date: Wed, 15 May 2024 00:39:21 +0100
From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc: "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
 "Nathan Chancellor" <nathan@kernel.org>,
 "Nick Desaulniers" <ndesaulniers@google.com>,
 "Bill Wendling" <morbo@google.com>, "Justin Stitt" <justinstitt@google.com>,
 "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
 linux-kernel@vger.kernel.org, llvm@lists.linux.dev,
 "Guenter Roeck" <linux@roeck-us.net>
Subject: Re: [PATCH 6/8] MIPS: Limit MIPS_MT_SMP support by ISA reversion
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=E5=9C=A82024=E5=B9=B45=E6=9C=8814=E6=97=A5=E4=BA=94=E6=9C=88 =E4=B8=8B=E5=
=8D=8810:38=EF=BC=8CMaciej W. Rozycki=E5=86=99=E9=81=93=EF=BC=9A
> On Fri, 2 Feb 2024, Jiaxun Yang wrote:
>
>> MIPS MT ASE is only available on ISA between Release 1 and Release 5.
>
>  R2+ only actually, as also evident from Kconfig...

Hi Maciej,

Long time no see :-)

There is nothing stopping us to run R1 kernel on R2 hardware, given that
those features are all detected at boot time. I understand MT was introd=
uced
at 34K which is R2.

I tested booting R1 kernel with MT on 1004Kc.

I believe we should give users flexibility on enjoying optional features
on kernel targeting lower ISA Rev.

>
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -2171,7 +2171,8 @@ config CPU_R4K_CACHE_TLB
>>  config MIPS_MT_SMP
>>  	bool "MIPS MT SMP support (1 TC on each available VPE)"
>>  	default y
>> -	depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICRO=
MIPS
>> +	depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
>> +	depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
>>  	select CPU_MIPSR2_IRQ_VI
>>  	select CPU_MIPSR2_IRQ_EI
>                    ^^^^^^
>  ... here.  I wish people looked beyond the line they change, sigh...

Both features (VI and VEIC) are probed at boot time. Selecting
them doesn't necessarily mean that CPU has those functions.

Thanks
- Jiaxun
>
>   Maciej

--=20
- Jiaxun