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Tue, 14 May 2024 18:20:07 -0700 Date: Tue, 14 May 2024 18:20:06 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH RFCv1 05/14] iommufd: Add IOMMUFD_OBJ_VIOMMU and IOMMUFD_CMD_VIOMMU_ALLOC Message-ID: References: <3aa9bc1df6a2ee58a03c6ea6ededbc210a2d23a8.1712978212.git.nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004683:EE_|LV3PR12MB9439:EE_ X-MS-Office365-Filtering-Correlation-Id: 859b7dd6-078a-4930-8b71-08dc747d31cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|7416005|376005|1800799015|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?LCCYxgg6ACJ7hLMuLHN2ZVm630wE1sNsEGF9CVZvEbnKDDmabMaKofiQSsK4?= =?us-ascii?Q?A6s1k2Xgfyody3ERvzCBAQoQGnUelNSkMo/Q0gS1w5HSMHDCIiOtUPCTyHYu?= =?us-ascii?Q?5bs5zbW7iPiW+2Y3q8VqOmt9S0mc2uiZFS6TS8UtHzPmyP4d6mWADJXj9j0d?= =?us-ascii?Q?Q4QUtOOeBqH/G/LZrmlHBuXJBlGxRc+rX7BZcF6/kVkngPQ/06/WFFmKIQFT?= =?us-ascii?Q?A055LX0N99YNLljbWNDCF3y2PZ2RP1vegVKBwAlLb4S3myne74wV0kNOemsU?= =?us-ascii?Q?TYMeIAiAjyRJImkxmHHxtrfC+NiRIcp5WcVfw/PIgkpgyJr9pYEZJqIRklVz?= =?us-ascii?Q?D/h4ZRbccvaR6q1HMDfm1cxB2PSfC5R9IoO1tT1FPz1yYjLJrmH6pLZq8D1U?= =?us-ascii?Q?yTEXTxbbo9K+GQg96Tg3h7Oh27NiW9UkLKJiUFisc0HJnv6gk7WZ8lEA/4VU?= =?us-ascii?Q?jcvHWV1dYunAgYvO1bMIEpLmzVQqc3Txjzm31wZXK3JIonQ2yOZ/sx9TG0+R?= =?us-ascii?Q?e3vGXWLJmOoMHm/R0F5m8LqqHrIE9JceGHd0FbGrDf6xGB7+kZeHjzbm604/?= =?us-ascii?Q?fKWmUFfZZvY3vF3IyPENVTsWLlmAAtrLj/k4+HEiBYvkXrv4rG0EqFlzkOT7?= =?us-ascii?Q?fy/b038R8V4Zsk7wowVWABWuPZFwLBB6L83ALa7pAoKnVGg9t6yBsPsb9GTR?= =?us-ascii?Q?RNBhmzUQuoFeh1K3lfpPrrGz/zc9sKunxoKaOGLeDdNqyTQIC8INp66GssYP?= =?us-ascii?Q?XT9d7wdvH0dBeY04HllZ/9fgGcIp7MoAahMCa4NIQTJKoLYqLRQUuEKBr098?= =?us-ascii?Q?7wFpq1m2JJ4X0s7vyXYJUvQE38qyq4X0e6lSdE/ZHQpg1TY7gu2nxN0Ez+Xl?= =?us-ascii?Q?EHux0LVMdkJeLsYTk6QbkPKAhiM9ALW37/DzsGdAgKOjhle2IPGrxcQm2QWN?= =?us-ascii?Q?Ydondc19U0qdTFim+EMdlaAz2ywd3Emr1gmmNvUXQLJxdDggBn+d5UeNjhgu?= =?us-ascii?Q?y/wkJ0v0jdJ+J/Co+QPGO/mENxpK/6HgBEMV1wyQI8grgkQ7kH/xP2orWrpp?= =?us-ascii?Q?3IraE5PgeJJ0SDllkAyXeZ4o0zdyfOSSchmDoO1xwYxvf4Npu31zwGB4vEFc?= =?us-ascii?Q?YxyZ2ECXJwhE3rd/pgRkDKYvDt5KyCpsrFpDVuJ/2L6Oz0vFikUieOxDXvL/?= =?us-ascii?Q?mH+euMWVlFWs9XEAofqtX1QkF9VO0j9GPCMppVCfKQ3igX4yDvjcEuXpzuK7?= =?us-ascii?Q?pqoVPnrbKNypOFyFp5m36YmghxpS674w70krzlj3xF8m0xVSPR7l5Io8Fab6?= =?us-ascii?Q?EHk4mbXDfX//30UCsVhiY4hCqRjvO6uyPOdERTvUjM1GCAKWh3ejPkexD5Le?= =?us-ascii?Q?JMD43YdGp36PaXRisnfBMnZYV63o?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(7416005)(376005)(1800799015)(36860700004)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2024 01:20:23.3180 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 859b7dd6-078a-4930-8b71-08dc747d31cd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004683.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9439 On Tue, May 14, 2024 at 12:38:57PM -0300, Jason Gunthorpe wrote: > > > > + > > > > +/** > > > > + * enum iommu_viommu_type - VIOMMU Type > > > > + * @IOMMU_VIOMMU_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension for SMMUv3 > > > > + */ > > > > +enum iommu_viommu_type { > > > > + IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, > > > > +}; > > > > > > At least the 241 line should be in a following patch > > > > It's for the "enum iommu_viommu_type" mentioned in the following > > structure. Yi told me that you don't like an empty enum, and he > > did something like this in HWPT_INVALIDATE series: > > https://lore.kernel.org/linux-iommu/20240111041015.47920-3-yi.l.liu@intel.com/ > > I suspect 0 should be reserved as a non-set value for some > basic sanity in all these driver type enums. We have an IOMMU_HWPT_DATA_NONE for HWPT_ALLOC to compatible with an S2 hwpt, since it doesn't need a data. Maybe we can have an IOMMU_VIOMMU_TYPE_DEFAULT to be 0, for an IOMMU driver (e.g. VT-d) that doesn't need to handle nor be aware of any viommu object? So, VMM can have a unified "attach-to-viommu" practice with different IOMMUs, v.s. some still doing "attach-to-s2"? > > > So, to make this all work perfectly we need approx the following > > > - S2 sharing across instances in ARM - meaning the VMID is allocated > > > at attach not domain alloc > > > - S2 hwpt is refcounted by the VIOMMU in the iommufd layer > > > - VIOMMU is refcounted by every nesting child in the iommufd layer > > > - The nesting child holds a pointer to both the S2 and the VIOMMU > > > (viommu optional) > > > - When the nesting child attaches to a device the STE will source the > > > VMID from the VIOMMU if present otherwise from the S2 > > > - "RID" attach (ie naked S2) will have to be done with a Nesting > > > Child using a vSTE that indicates Identity. Then the attach logic > > > will have enough information to get the VMID from the VIOMMU > > > > What is this RID attach (naked S2) case? S1DSS_BYPASS + SVA? > > No, when the guest installs a vSTE that simply says bypass with no CD > table pointer. That should result in a pSTE that is the S2 with on CD > pointer. > > I was originally thinking that the VMM would simply directly attach > the S2 HWPT in this caes, but given the above issue with the VMID lifetime > it makes more sense to 'attach' the viommu which holds the correct > VMID. > > The issue with direct attach the S2 HWPT is the VMID lifetime, as it > would have to borrow the VMID from the viommu but then the lifetime > becomes more complex as it has to live beyond VIOMMU destruction. Not > unsolvable but it seems easier to just avoid it entirely. That makes a lot sense. I'd need to go through QEMU code and see how we will accommodate these two more naturally: likely the QEMU core should allocate an S2 HWPT for a VM, while the viommu code should allocate a VIOMMU for each instance. Thanks Nicolin