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From: "Wang, Xiao W" <xiao.w.wang@intel.com>
To: Andrew Jones <ajones@ventanamicro.com>
CC: "paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>, "aou@eecs.berkeley.edu"
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	"xi.wang@gmail.com" <xi.wang@gmail.com>, "bjorn@kernel.org"
	<bjorn@kernel.org>, "ast@kernel.org" <ast@kernel.org>, "daniel@iogearbox.net"
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	<pulehui@huawei.com>, "Li, Haicheng" <haicheng.li@intel.com>,
	"conor@kernel.org" <conor@kernel.org>, Ben Dooks <ben.dooks@codethink.co.uk>
Subject: RE: [PATCH v2] riscv, bpf: Optimize zextw insn with Zba extension
Thread-Topic: [PATCH v2] riscv, bpf: Optimize zextw insn with Zba extension
Thread-Index: AQHao0tSYAL6LqZaWUWtv7jZE6ZoR7GVZY4AgADuVMCAAG0hAIABKwRQ
Date: Wed, 15 May 2024 07:38:17 +0000
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> -----Original Message-----
> From: Andrew Jones <ajones@ventanamicro.com>
> Sent: Tuesday, May 14, 2024 9:37 PM
> To: Wang, Xiao W <xiao.w.wang@intel.com>
> Cc: paul.walmsley@sifive.com; palmer@dabbelt.com;
> aou@eecs.berkeley.edu; luke.r.nels@gmail.com; xi.wang@gmail.com;
> bjorn@kernel.org; ast@kernel.org; daniel@iogearbox.net; andrii@kernel.org=
;
> martin.lau@linux.dev; eddyz87@gmail.com; song@kernel.org;
> yonghong.song@linux.dev; john.fastabend@gmail.com; kpsingh@kernel.org;
> sdf@google.com; haoluo@google.com; jolsa@kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; bpf@vger.kernel.=
org;
> pulehui@huawei.com; Li, Haicheng <haicheng.li@intel.com>;
> conor@kernel.org; Ben Dooks <ben.dooks@codethink.co.uk>
> Subject: Re: [PATCH v2] riscv, bpf: Optimize zextw insn with Zba extensio=
n
>=20
> On Tue, May 14, 2024 at 07:36:04AM GMT, Wang, Xiao W wrote:
> >
> >
> > > -----Original Message-----
> > > From: Andrew Jones <ajones@ventanamicro.com>
> > > Sent: Tuesday, May 14, 2024 12:53 AM
> > > To: Wang, Xiao W <xiao.w.wang@intel.com>
> > > Cc: paul.walmsley@sifive.com; palmer@dabbelt.com;
> > > aou@eecs.berkeley.edu; luke.r.nels@gmail.com; xi.wang@gmail.com;
> > > bjorn@kernel.org; ast@kernel.org; daniel@iogearbox.net;
> andrii@kernel.org;
> > > martin.lau@linux.dev; eddyz87@gmail.com; song@kernel.org;
> > > yonghong.song@linux.dev; john.fastabend@gmail.com;
> kpsingh@kernel.org;
> > > sdf@google.com; haoluo@google.com; jolsa@kernel.org; linux-
> > > riscv@lists.infradead.org; linux-kernel@vger.kernel.org;
> bpf@vger.kernel.org;
> > > pulehui@huawei.com; Li, Haicheng <haicheng.li@intel.com>;
> > > conor@kernel.org
> > > Subject: Re: [PATCH v2] riscv, bpf: Optimize zextw insn with Zba exte=
nsion
> > >
> > > On Sat, May 11, 2024 at 10:34:36AM GMT, Xiao Wang wrote:
> > > > The Zba extension provides add.uw insn which can be used to impleme=
nt
> > > > zext.w with rs2 set as ZERO.
> > > >
> > > > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> > > > ---
> > > > v2:
> > > > * Add Zba description in the Kconfig. (Lehui)
> > > > * Reword the Kconfig help message to make it clearer. (Conor)
> > > > ---
> > > >  arch/riscv/Kconfig       | 22 ++++++++++++++++++++++
> > > >  arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> > > >  2 files changed, 40 insertions(+)
> > > >
> > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > > index 6bec1bce6586..e262a8668b41 100644
> > > > --- a/arch/riscv/Kconfig
> > > > +++ b/arch/riscv/Kconfig
> > > > @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> > > >  	  preemption. Enabling this config will result in higher memory
> > > >  	  consumption due to the allocation of per-task's kernel Vector
> > > context.
> > > >
> > > > +config TOOLCHAIN_HAS_ZBA
> > > > +	bool
> > > > +	default y
> > > > +	depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zb=
a)
> > > > +	depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_z=
ba)
> > > > +	depends on LLD_VERSION >=3D 150000 || LD_VERSION >=3D 23900
> > > > +	depends on AS_HAS_OPTION_ARCH
> > > > +
> > > >  config TOOLCHAIN_HAS_ZBB
> > > >  	bool
> > > >  	default y
> > > > @@ -601,6 +609,20 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
> > > >  	def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
> > > >  	depends on AS_HAS_OPTION_ARCH
> > > >
> > > > +config RISCV_ISA_ZBA
> > > > +	bool "Zba extension support for bit manipulation instructions"
> > > > +	depends on TOOLCHAIN_HAS_ZBA
> > >
> > > We handcraft the instruction, so why do we need toolchain support?
> >
> > Good point, we don't need toolchain support for this bpf jit case.
> >
> > >
> > > > +	depends on RISCV_ALTERNATIVE
> > >
> > > Also, while riscv_has_extension_likely() will be accelerated with
> > > RISCV_ALTERNATIVE, it's not required.
> >
> > Agree, it's not required. For this bpf jit case, we should drop these t=
wo
> dependencies.
> >
> > BTW, Zbb is used in bpf jit, the usage there also doesn't depend on too=
lchain
> and
> > RISCV_ALTERNATIVE, but the Kconfig for RISCV_ISA_ZBB has forced the
> dependencies
> > due to Zbb assembly programming elsewhere.
> > Maybe we could just dynamically check the existence of RISCV_ISA_ZB*
> before jit code
> > emission? or introduce new config options for bpf jit? I prefer the fir=
st
> method and
> > welcome any comments.
>=20
> My preferences is to remove as much of the TOOLCHAIN_HAS_ stuff as
> possible. We should audit the extensions which have them to see if
> they're really necessary. I don't mind depending on RISCV_ALTERNATIVE,
> since it's almost required for riscv at this point anyway.

I go through all the existing TOOLCHAIN_HAS_* stuff, all of them are
helpful for compiling the corresponding assembly code. So they're really
necessary.

For this patch, I would drop the two dependencies for RISCV_ISA_ZBA Kconfig=
,
as the jit doesn't depend on them.

BRs,
Xiao

>=20
> Thanks,
> drew
>=20
> >
> > Thanks,
> > Xiao
> >
> > [...]
> > > >  {
> > > > +	if (rvzba_enabled()) {
> > > > +		emit(rvzba_zextw(rd, rs), ctx);
> > > > +		return;
> > > > +	}
> > > > +
> > > >  	emit_slli(rd, rs, 32, ctx);
> > > >  	emit_srli(rd, rd, 32, ctx);
> > > >  }
> > > > --
> > > > 2.25.1
> > > >
> > >
> > > Thanks,
> > > drew