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Wed, 15 May 2024 11:46:47 GMT Received: from [10.253.15.49] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 15 May 2024 04:46:46 -0700 Message-ID: <38fcae90-f3f9-4b19-8b36-53ab93dc0953@quicinc.com> Date: Wed, 15 May 2024 19:46:28 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] bus: mhi: host: Add Foxconn SDX72 related support To: Manivannan Sadhasivam , Slark Xiao CC: , , , References: <20240510032657.789629-1-slark_xiao@163.com> <20240514143741.GA2306@thinkpad> <541de8e4.1600.18f79de44f3.Coremail.slark_xiao@163.com> <20240515074119.GA2445@thinkpad> Content-Language: en-US From: Qiang Yu In-Reply-To: <20240515074119.GA2445@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TVmkk0hyM7JnVNjh-IkG_A4pAMjOkS-5 X-Proofpoint-ORIG-GUID: TVmkk0hyM7JnVNjh-IkG_A4pAMjOkS-5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-15_06,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 clxscore=1011 priorityscore=1501 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405150081 On 5/15/2024 3:41 PM, Manivannan Sadhasivam wrote: > + Qiang > > On Wed, May 15, 2024 at 09:29:20AM +0800, Slark Xiao wrote: >> At 2024-05-14 22:37:41, "Manivannan Sadhasivam" wrote: >>> On Fri, May 10, 2024 at 11:26:57AM +0800, Slark Xiao wrote: >>>> Align with Qcom SDX72, add ready timeout item for Foxconn SDX72. >>>> And also, add firehose support since SDX72. >>>> >>>> Signed-off-by: Slark Xiao >>>> --- >>>> drivers/bus/mhi/host/pci_generic.c | 31 ++++++++++++++++++++++++++++++ >>>> 1 file changed, 31 insertions(+) >>>> >>>> diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c >>>> index 08844ee79654..0fd94c193fc6 100644 >>>> --- a/drivers/bus/mhi/host/pci_generic.c >>>> +++ b/drivers/bus/mhi/host/pci_generic.c >>>> @@ -399,6 +399,8 @@ static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { >>>> MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), >>>> MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), >>>> MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), >>>> + MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), >>>> + MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), >>> This means SDX55 is also supporting FIREHOSE channels, which is not true I >>> believe. >> Actually, I just verified it with my sdx55 and the answer is Yes. These channels >> are common settings for Qcom device which support PCIe mode. BTW, the >> default settings of Qcom and Quectel support firehose for their sdx55 products. > Qiang, can you please confirm that SDX55 supports FIREHOSE channels? Hi Mani Yes, SDX55 supports FIREHOSE channels. Thanks, Qiang > >>>> MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), >>>> MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), >>>> }; >>>> @@ -419,6 +421,16 @@ static const struct mhi_controller_config modem_foxconn_sdx55_config = { >>>> .event_cfg = mhi_foxconn_sdx55_events, >>>> }; >>>> >>>> +static const struct mhi_controller_config modem_foxconn_sdx72_config = { >>>> + .max_channels = 128, >>>> + .timeout_ms = 20000, >>>> + .ready_timeout_ms = 50000, >>>> + .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), >>>> + .ch_cfg = mhi_foxconn_sdx55_channels, >>>> + .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), >>>> + .event_cfg = mhi_foxconn_sdx55_events, >>>> +}; >>>> + >>>> static const struct mhi_pci_dev_info mhi_foxconn_sdx24_info = { >>>> .name = "foxconn-sdx24", >>>> .config = &modem_foxconn_sdx55_config, >>>> @@ -448,6 +460,16 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx65_info = { >>>> .sideband_wake = false, >>>> }; >>>> >>>> +static const struct mhi_pci_dev_info mhi_foxconn_sdx72_info = { >>>> + .name = "foxconn-sdx72", >>>> + .edl = "qcom/sdx72m/xbl_s_devprg_ns.melf", >>> What is '.melf'? Is the firmware available somewhere? Did you plan to upstream >>> it to linux-firmware? >>> >> This file similar with "edl.mbn". In SDX72 product, the default "edl" file name is >> "xbl_s_devprg_ns.melf". Currently we don't plan to upstream it to linux-firmware >> since 2 reasons: 1: we share the same fold name sdx72m with qcom or other vendors >> 2: this file may be changed since sdx72 product still under developing in our side. we >> may change the base line according to QCOM release. > Then I would ask you to add support when you have a stable firmware. I do not > want to change the firmware name after some time as it will confuse users. > > - Mani >