Received-SPF: pass (google.com: domain of linux-kernel+bounces-180353-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
Date: Wed, 15 May 2024 17:43:04 -0300
From: Jason Gunthorpe <jgg@nvidia.com>
To: Yan Zhao <yan.y.zhao@intel.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org,
	alex.williamson@redhat.com, kevin.tian@intel.com,
	iommu@lists.linux.dev, pbonzini@redhat.com, seanjc@google.com,
	dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org,
	tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com,
	corbet@lwn.net, joro@8bytes.org, will@kernel.org,
	robin.murphy@arm.com, baolu.lu@linux.intel.com, yi.l.liu@intel.com
Subject: Re: [PATCH 5/5] iommufd: Flush CPU caches on DMA pages in
 non-coherent domains
Message-ID: <ZkUeWAjHuvIhLcFH@nvidia.com>
References: <20240507061802.20184-1-yan.y.zhao@intel.com>
 <20240507062212.20535-1-yan.y.zhao@intel.com>
 <20240509141332.GP4650@nvidia.com>
 <Zj3UuHQe4XgdDmDs@yzhao56-desk.sh.intel.com>
 <20240510132928.GS4650@nvidia.com>
 <ZkHEsfaGAXuOFMkq@yzhao56-desk.sh.intel.com>
 <ZkN/F3dGKfGSdf/6@nvidia.com>
 <ZkRe/HeAIgscsYZw@yzhao56-desk.sh.intel.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <ZkRe/HeAIgscsYZw@yzhao56-desk.sh.intel.com>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?VIM7ZmdWIS7LLT2LLau3MV7i3HBXhk+gRAibJvXvHrunTx4H9V/nBpHhdJdh?=
 =?us-ascii?Q?1WVWYKk6euaCB0P17rTb2qMGZjRV8cYDOldMIdT5aDsI9Am2t+wIV3uK2pR7?=
 =?us-ascii?Q?lgfVFN++JmLVBjvkhNtRNrhdHvWxQ09OHXNoqt5ePlBOEaX+zUdmF0Fa4olX?=
 =?us-ascii?Q?heoPEdTXh+ggZwRn2KWA4zjNXfyU+AndHm3Pm0aABf2iXLoYQqy3SlBy3Y4c?=
 =?us-ascii?Q?5YPE4MPNgwNC8vzmI0Ei5ZoQMhusHr39xm4oyJsUQB0LtQ0u3gvRXFiFdIOb?=
 =?us-ascii?Q?2mburGhXZj7P/ls6xY8hZeWp3Q8WbZY2Wiha23NB01s9m1a+nTJX7RCBoHV7?=
 =?us-ascii?Q?QVg2CISHc1c1549BYauWCcCoDNlq3kkAICVsZgne6UPxba9u2uYRo+CEXYOw?=
 =?us-ascii?Q?xB0UD14NOojGVgqnqlrYlVVYCtBbK00xSrC5/SQbricXRoqWOt0E8JS6UZHV?=
 =?us-ascii?Q?snyAvnQYxh+FtuoZJIiSsdWTrg+Z36LszgCOTnYCrLeP8fyMG8vJjKFfYiw3?=
 =?us-ascii?Q?OoxozXg1QcJHrlRS5h7CZi/ufrbkntE0s8mx8kEdO4CPz9ONf/pF2lir8njW?=
 =?us-ascii?Q?Dld2fN7hYE9lmooqUUL07Uptdg0e6z94Vi3x52TKE6Yhq9mq3rPBOGvbtx8E?=
 =?us-ascii?Q?ZXKtB3gU1Af2ludKbMs4k9We6ZqkfkUItLAPKbFDnreph6Ly5Ct+qVNQNo5H?=
 =?us-ascii?Q?2PWZZKjFKcN/NTJETYTs36wnennU9gZVxvo/4rCb2JhmMHGsKESeRl0C0Ala?=
 =?us-ascii?Q?whLgAAzCQWTRAZUBFhQBqTYbBItF/BT/LAE4gjvjQ7ZaKQoLw+t3Fe82WLO9?=
 =?us-ascii?Q?onhtOyr/fbD43gOu+wr1Ey1Tc/UXkxje69fB2iCMdQaMbWQBL0/p6BsJc5e9?=
 =?us-ascii?Q?wkDQI4WKnzkuxszbzdh+9jUgFOWLL0pfY7ThIkc5otMTgOcIeTLHpjwHvLL4?=
 =?us-ascii?Q?mK+ojBgD/syX+lixsFJegZHw3XSzKN7EU0jRZiC7QQoUQEA/HbcLJv20XQYn?=
 =?us-ascii?Q?BYJilmVucs2+csjlan3W90zY7/laujBmGc12G+au4g7Q74zq0Yeqnklhaxu5?=
 =?us-ascii?Q?arM1gwYtCFPKnXOU7IlSLDb6dE7BekPygYxUw244qcUxJjdFywB2CH393mYW?=
 =?us-ascii?Q?Gd9NKDd3ZDELLGvA8xw9QCSHyO4TMBshUjgYHJlwJCXJ/uNO9DBCG6mXMcGv?=
 =?us-ascii?Q?IQdq8ALzgTxgviF3omg3c2Vjn32vpfO28QJO3b565IqFstlbE7+xD1Nxx2KF?=
 =?us-ascii?Q?feL4AhsEHKeHy40fhi6Tn4i+9u3ndhvGUs/AluCQcsc0PCkomPjTfRlvU9/3?=
 =?us-ascii?Q?Rno62nPxs/XaX/+eimvLpT994w2sfkNBxGxINb/Q2TmQRMALyXkGN+W2Ogr8?=
 =?us-ascii?Q?yZ4n5cAeJ0Lxi0jozyjMnXz4F81wn3cai0VTs7twMOaa5CRj85yBpVedlE9x?=
 =?us-ascii?Q?H2GnL5iS1H3iDRAsFqJ+bx3LFTO8WQ4AWHOE286Xa1cw0jl7s4x/TyP56gnE?=
 =?us-ascii?Q?21lQZ68JkpjsvYXEP4C/Z5Mn6tkI4qpOiR9AxklpWvH/O0rTfm9mr5Iy/GQ5?=
 =?us-ascii?Q?AeUJoayLnlVq1jqCFAQ=3D?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: d5936ccb-5813-4b83-31ad-08dc751f9f1f
X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3849.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2024 20:43:05.4919
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: tV2/bfQPV233TqDApcpdmUdJdayD9Y3BSDA34rlt9GCAynUjZGHXSlafj/AC/uQ0
X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7513

On Wed, May 15, 2024 at 03:06:36PM +0800, Yan Zhao wrote:

> > So it has to be calculated on closer to a page by page basis (really a
> > span by span basis) if flushing of that span is needed based on where
> > the pages came from. Only pages that came from a hwpt that is
> > non-coherent can skip the flushing.
> Is area by area basis also good?
> Isn't an area either not mapped to any domain or mapped into all domains?

Yes, this is what the span iterator turns into in the background, it
goes area by area to cover things.

> But, yes, considering the limited number of non-coherent domains, it appears
> more robust and clean to always flush for non-coherent domain in
> iopt_area_fill_domain().
> It eliminates the need to decide whether to retain the area flag during a split.

And flush for pin user pages, so you basically always flush because
you can't tell where the pages came from.

Jason