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Subject: Re: [PATCH 0/2] riscv: Allow vlenb to be probed from DT
From: Jessica Clarke <jrtc27@jrtc27.com>
In-Reply-To: <ZkVAYeNnvj99YHXt@ghost>
Date: Thu, 16 May 2024 01:58:29 +0100
Cc: Conor Dooley <conor@kernel.org>,
 Paul Walmsley <paul.walmsley@sifive.com>,
 Palmer Dabbelt <palmer@dabbelt.com>,
 Albert Ou <aou@eecs.berkeley.edu>,
 Palmer Dabbelt <palmer@sifive.com>,
 linux-riscv <linux-riscv@lists.infradead.org>,
 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>,
 LKML <linux-kernel@vger.kernel.org>,
 Conor Dooley <conor.dooley@microchip.com>
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Message-Id: <6DDF33DF-07D6-4230-8674-F91A91660686@jrtc27.com>
References: <20240515-add_vlenb_to_dt-v1-0-4ebd7cba0aa1@rivosinc.com>
 <A9EDD470-B8EC-4644-82A0-7444729EF885@jrtc27.com> <ZkVAYeNnvj99YHXt@ghost>
To: Charlie Jenkins <charlie@rivosinc.com>

On 16 May 2024, at 00:08, Charlie Jenkins <charlie@rivosinc.com> wrote:
>=20
> On Wed, May 15, 2024 at 11:25:16PM +0100, Jessica Clarke wrote:
>> On 15 May 2024, at 22:50, Charlie Jenkins <charlie@rivosinc.com> =
wrote:
>>>=20
>>> The kernel currently requires all harts to have the same value in =
the
>>> vlenb csr that is present when a hart supports vector. In order to =
read
>>> this csr, the kernel needs to boot the hart. Adding vlenb to the DT =
will
>>> allow the kernel to detect the inconsistency early and not waste =
time
>>> trying to boot harts that it doesn't support.
>>=20
>> That doesn=E2=80=99t seem sufficient justification to me. If it can =
be read
>> from the hardware, why should we have to put it in the FDT? The whole
>> point of the FDT is to communicate the hardware configuration that
>> isn=E2=80=99t otherwise discoverable.
>=20
> Yes you are correct in that vlenb is discoverable on any conforming
> chip. However, the motivation here is for making decisions about how =
to
> boot a hart before it is booted. By placing it in the device tree, we
> are able to disable vector before the chip is booted instead of trying
> to boot the chip with vector enabled only to disable it later. In both
> cases when there is different vlenb on different harts, all harts =
still
> boot and the outcome is that vector is disabled. The difference is =
that
> with the DT entry, no vector setup code needs to be ran on a booting
> hart when the outcome will be that vector is not enabled.

Why does vlen get this special treatment? You could make exactly the
same argument for the number of asid bits. The precedent in the kernel,
whether RISC-V or other architectures, is to not do this. You can
detect it, so you should, especially since optimising for an
exceptional, unexpected error case is not worthwhile.

>> As for T-HEAD stuff, if they need it they can have a custom property.
>> Though naively I=E2=80=99d assume there=E2=80=99s a way to avoid it =
still...
>=20
> T-Head does not expose vlenb on all of their chips so I do not know of
> any other way of getting the vlenb without having it be provided in a
> DT. That was the motivation for this patch in the first place, but
> making this available to all vendors allows optimizations to happen
> during boot.

How does userspace read it then? But if T-HEAD need it, that means it
should be a thead,vlen, not a riscv,vlen.

Jess