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From: yunhui cui <cuiyunhui@bytedance.com>
Date: Thu, 16 May 2024 10:44:31 +0800
Message-ID: <CAEEQ3wkpKHryCcNXpDXCi5tsfz2ryc9y_7JbvREg3D2MMic2ng@mail.gmail.com>
Subject: Re: [External] Re: [PATCH v5 2/3] riscv: cacheinfo: initialize
 cacheinfo's level and type from ACPI PPTT
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: rafael@kernel.org, lenb@kernel.org, linux-acpi@vger.kernel.org, 
	linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, 
	sunilvl@ventanamicro.com, aou@eecs.berkeley.edu, 
	linux-riscv@lists.infradead.org, bhelgaas@google.com, james.morse@arm.com, 
	jhugo@codeaurora.org, jeremy.linton@arm.com, john.garry@huawei.com, 
	Jonathan.Cameron@huawei.com, pierre.gondois@arm.com, tiantao6@huawei.com, 
	Conor Dooley <conor.dooley@microchip.com>, Sudeep Holla <sudeep.holla@arm.com>
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Hi Palmer,

Gentle ping ...

On Fri, May 10, 2024 at 5:09=E2=80=AFPM yunhui cui <cuiyunhui@bytedance.com=
> wrote:
>
> Hi Palmer,
>
> There are already related Reviewed-by, Gentle ping...
>
> On Thu, May 9, 2024 at 11:27=E2=80=AFPM Sudeep Holla <sudeep.holla@arm.co=
m> wrote:
> >
> > On Thu, May 09, 2024 at 03:32:59PM +0800, Yunhui Cui wrote:
> > > Before cacheinfo can be built correctly, we need to initialize level
> > > and type. Since RISC-V currently does not have a register group that
> > > describes cache-related attributes like ARM64, we cannot obtain them
> > > directly, so now we obtain cache leaves from the ACPI PPTT table
> > > (acpi_get_cache_info()) and set the cache type through split_levels.
> > >
> > > Suggested-by: Jeremy Linton <jeremy.linton@arm.com>
> > > Suggested-by: Sudeep Holla <sudeep.holla@arm.com>
> >
> > I am not sure why you have not added my reviewed-by as I was happy with
> > v3 onwards IIRC. Anyways, I will give it again =F0=9F=98=84
> >
> > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> >
> > --
> > Regards,
> > Sudeep
>
> Thanks=EF=BC=8C
> Yunhui

Thanks,
Yunhui