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Date: Thu, 16 May 2024 10:33:21 +0200
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Richard Weinberger <richard@nod.at>, Vignesh Raghavendra
 <vigneshr@ti.com>, linux-mtd@lists.infradead.org,
 linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/3] mtd: nand: mxc_nand: support software ECC
Message-ID: <20240516103321.25b49576@xps-13>
In-Reply-To: <ZkRyTT7FcDQ-5UeV@pengutronix.de>
References: <20240514-mtd-nand-mxc-nand-exec-op-v3-0-3e6f45fd3d82@pengutronix.de>
	<20240514-mtd-nand-mxc-nand-exec-op-v3-3-3e6f45fd3d82@pengutronix.de>
	<ZkRyTT7FcDQ-5UeV@pengutronix.de>
Organization: Bootlin
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Hi Sascha,

> > +	/*
> > +	 * During a page write the i.MX NAND controller will read 512b from
> > +	 * main_area0 SRAM, then oob_per_subpage bytes from spare0 SRAM, then
> > +	 * 512b from main_area1 SRAM and so on until the full page is written.
> > +	 * For software ECC we want to have a 1:1 mapping between the raw page
> > +	 * data on the NAND chip and the view of the NAND core. This is
> > +	 * necessary to make the NAND_CMD_RNDOUT read the data it expects.
> > +	 * To accomplish this we have to write the data in the order the cont=
roller
> > +	 * reads it. This is reversed in copy_page_from_sram() below.
> > +	 */
> > +	for (i =3D 0; i < no_subpages; i++) {
> > +		memcpy16_toio(host->main_area0 + i * 512, buf, 512);
> > +		buf +=3D 512;
> > +
> > +		memcpy16_toio(host->spare0 + i * host->devtype_data->spare_len, buf,
> > +			      oob_per_subpage);
> > +		buf +=3D oob_per_subpage;
> > +	}
> > +} =20
>=20
> I noticed the nandbiterr test won't work with this. It needs the following
> fixup. The problem is that the core wants to write only user data
> without OOB, so we have to make sure the remaining SRAM is filled up
> with 0xff.

Yes. I looked rapidly at the diff, looks ok.

Thanks,
Miqu=C3=A8l