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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?iso-8859-1?Q?eAIQFM6v/ROi/D5wcic/tIduqqjfgS7W/ompQHa4AcrMqzuN0AAt2lOpu2?= =?iso-8859-1?Q?kZVQiGzqMeXCiseiA5DFIzl4yxpArWjEF/ngV8Spgep3g2q/2zs1te64ir?= =?iso-8859-1?Q?XFzmZfYYeQrTWH76nP6t0tlsIFtSgog+Er5vnzKTuDCx23CxJGD0NYa5mO?= =?iso-8859-1?Q?eUjOPquyD62lDx555s2fjwG48IKgvL7BQxfLvcRKkBxJJ9YWM9mHoxVRAQ?= =?iso-8859-1?Q?WjsX+jnejJH+YnFepY1iikij4zr0RSkFHBby2T1tEfL4DkptVeWsqLITWL?= =?iso-8859-1?Q?wMkiY1G7srNUmrf+S8019zc8iwFZW1oLxUPeN7NLEL0w/T1UGogTffoD0b?= =?iso-8859-1?Q?Yw4KshxnJSk1AjJeWjckPVpVDADQgO/UB5JO/SSvt1z08qEBoA3yr0cDv5?= =?iso-8859-1?Q?ZsUR5cLrFPIAfOHv+RzqIy4WfF/gv4W86H1evZlId5j/0NFgxdM/+9r6Q6?= =?iso-8859-1?Q?VW1eTuPVpvLpU4dGX5n+d0zdHlSvgLDY2ya8hP+jOQmdgosOcqcIZKOJNj?= =?iso-8859-1?Q?e0voPcm+MXC4KWBDdh8hdhgyD2tMnMJ+uau6LMmoh/s8NIkSe/9SzhxVbU?= =?iso-8859-1?Q?dQQ4SRrY1AIjIld86XpNHHChyNMxJY6Q2qOqX1iEp7YwhxV34eooXEISJd?= =?iso-8859-1?Q?lry1BeTI6yM7IHH6Z4QEQL4ufE2U1om46hmWc8ldJihCHtYAfO8vLRmjhM?= =?iso-8859-1?Q?HlvNW2WYlh0u/+5pAGlhJfOu71yF3MuQo0MhM731GX6XTG48jRnPpJTmsc?= =?iso-8859-1?Q?KccRm/SOEHkUFGbwzgCTkwR1jKFQLnEnppuQymk9jCMBZcGECGWPgWSV65?= =?iso-8859-1?Q?sj5HU6XVowKY+oNPxFqU6U6y4JCR9Tk7ynMaGayvIiJ4C+HOt5gwwjPTwO?= =?iso-8859-1?Q?0uemAADngYhHuFPfUUV3LXf2fAUTKXCDuZ2D63G7erHMaMMvjZoVmSsWe9?= =?iso-8859-1?Q?n3yvvgTjhMgkmSPEdz3AZ5A+hEHvKm5GzXAgxfSo47qNm4KZduM4g3bQKT?= =?iso-8859-1?Q?mG2YrvYA/pum+PGliF/xzDBfStnAQU7fKnXmpQB+1kgkp1oA4Z0vOmfBG1?= =?iso-8859-1?Q?9gWwepVLFZptnbQrn4DXi4npyPUqa7nHAELKVWzCqiqyTc6Ih5nXYhqSEu?= =?iso-8859-1?Q?GXvEDuiftifHn8CEwzdNtjRYb4et/4GXiuUaGcBXL8OWedJ/yj3041sHHn?= =?iso-8859-1?Q?Qsx32mqmPjFugmeMd2HqjX6X3ku7qSwIen8sTgrYyBrHi6g6o4Vug8r0AK?= =?iso-8859-1?Q?fbKxbpLQSe4f3teG2gJyCTQHmLKWHqD1cKFjNOINGFVbX+zm22sI3DMKF/?= =?iso-8859-1?Q?mr0aGNTDuuSPsnaZgG0vvqPOBfyEDSjm3ujeMn8So6BdhlkrmxNRxX90ex?= =?iso-8859-1?Q?ATrYyRLXp9aA6fktEmuxQ1JgzJCGnHYs7bQ7tBvePOx6nAxH0SSa67yzjH?= =?iso-8859-1?Q?ywY4/RJ0F+4v5qH5uTslX7f9flumCSjqIGml0MmMBE/2SQtVZcjvQxXKsR?= =?iso-8859-1?Q?bCbQ6DT95XLLc/ViCHkOdDlCdx6/65z1xi331WXKU3rM8z7D6E4bLBCp97?= =?iso-8859-1?Q?nLrRQTrpsRdM0TtuUjrHOuNLFfO9P4wAH3KqbZQjbvV2kET2u6rQHKt9mN?= =?iso-8859-1?Q?IpUfD+zrSS5XnlpwP34020vsPyTgXKzdYfc0JnpGNBQnkwTUpuykuS+0vL?= =?iso-8859-1?Q?RXmFxfz7xDRPanmPnbo=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: b933eb57-1b61-4aab-2184-08dc7586866a X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6231.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:59:42.2614 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pcngXLLQlyUQD3eAJvj+kz5vKGh5px0tm2nViEBpae1ir28+cgniXjf1VSGMRP3XWFW+64lFN7aJkM7Vu2AqKGXj54VfcuG5RbMKKc2vLfA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR11MB6337 X-OriginatorOrg: intel.com On 2024-05-15 at 15:23:23 -0700, Tony Luck wrote: >The sanity check that RMIDs are being read from a CPU listed in the >the cpu_mask for the domain is incorrect when summing across multiple the the cpu_mask -> the cpu_mask? >SNC domains. It is safe to read the RMID from any CPU that shares the >same L3 cache instance. > >Signed-off-by: Tony Luck >--- > arch/x86/kernel/cpu/resctrl/monitor.c | 15 +++++++++++++-- > 1 file changed, 13 insertions(+), 2 deletions(-) > >diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c >index 668d2fdf58cd..e4b92c7af71d 100644 >--- a/arch/x86/kernel/cpu/resctrl/monitor.c >+++ b/arch/x86/kernel/cpu/resctrl/monitor.c >@@ -15,6 +15,7 @@ > * Software Developer Manual June 2016, volume 3, section 17.17. > */ > >+#include > #include > #include > #include >@@ -281,8 +282,18 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *d, > > resctrl_arch_rmid_read_context_check(); > >- if (!cpumask_test_cpu(smp_processor_id(), &d->hdr.cpu_mask)) >- return -EINVAL; >+ if (r->mon_scope == r->mon_display_scope) { >+ if (!cpumask_test_cpu(smp_processor_id(), &d->hdr.cpu_mask)) >+ return -EINVAL; >+ } else { >+ /* >+ * SNC: OK to read events on any CPU sharing same L3 >+ * cache instance. >+ */ >+ if (d->display_id != get_cpu_cacheinfo_id(smp_processor_id(), >+ r->mon_display_scope)) >+ return -EINVAL; >+ } > > ret = __rmid_read(rmid, eventid, &msr_val); > if (ret) >-- >2.44.0 > -- Kind regards Maciej Wiecz?r-Retman