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Date: Thu, 16 May 2024 12:16:45 +0300
From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Esther Shimanovich <eshimanovich@chromium.org>
Cc: Lukas Wunner <lukas@wunner.de>,
	Mario Limonciello <mario.limonciello@amd.com>,
	Dmitry Torokhov <dmitry.torokhov@gmail.com>,
	Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Rajat Jain <rajatja@google.com>
Subject: Re: [PATCH v4] PCI: Relabel JHL6540 on Lenovo X1 Carbon 7,8
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In-Reply-To: <CA+Y6NJF+sJs_zQEF7se5QVMBAhoXJR3Y7x0PHfnBQZyCBbbrQg@mail.gmail.com>

Hi,

On Wed, May 15, 2024 at 02:53:54PM -0400, Esther Shimanovich wrote:
> > For the clarity, Intel integrated Thunderbolt 3 controller first in Ice
> > Lake, then Thunderbolt 4 controller in Tiger Lake and forward (Alder
> > Lake, Raptor Lake, Meteor Lake). Anything else, including Comet Lake and
> > the like are using discrete controllers such as Alpine Ridge, Titan
> > Ridge (both Thunderbolt 3) and Maple Ridge (Thunderbolt 4), and Barlow
> > Ridge (Thunderbolt 5) where the controller is either soldered on the
> > motherboard or connected to a PCIe slot.
> 
> Thanks for the explanation!
> This patch worked smoothly on the device I tried. I'd be happy to go
> forward with this patch, and test it on more devices.
> Is that fine? Or should I try something else on the build I made with
> Lukas's commits?

I suggest trying on more devices just to be sure it covers all of them.