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AJvYcCVI8Ri47RvtT8ZILRgSjdogk1yiVpFISXFBDcKbUGye3eQtYBEgz+R1BZf72RdFemAYXHJ0aJdvltcT3UWrlgKt6khWV5bsY+fXOqKSLoiFQ9R1BO065S84hQ6G2HzpwAv0PHuL5e2a5A== X-Gm-Message-State: AOJu0Yy0VAxsy1Xvbc5TH/Quy4H6QyrfCpQyTqRJxj6ByJ7L8VckEmWQ WKZTBzbsa/e/L5PekxJYJwPlOeJ5WVJ6o+RQBhB3iTDT+yA9jf5k X-Received: by 2002:a05:600c:198a:b0:41b:fc3a:f1ef with SMTP id 5b1f17b1804b1-41feac5a3damr136908115e9.33.1715892095152; Thu, 16 May 2024 13:41:35 -0700 (PDT) Received: from localhost.localdomain ([188.25.209.252]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733c2b8f7fsm10859828a12.66.2024.05.16.13.41.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 May 2024 13:41:34 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Shawn Guo , Philipp Zabel , Liu Ying , Sascha Hauer Cc: laurentiu.mihalcea@nxp.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: imx8ulp: add AVD-SIM node Date: Thu, 16 May 2024 23:40:31 +0300 Message-Id: <20240516204031.171920-5-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240516204031.171920-1-laurentiumihalcea111@gmail.com> References: <20240516204031.171920-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Laurentiu Mihalcea Add node for imx8ulp's AVD-SIM. This also includes its children. Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index c4a0082f30d3..5135d98dc6f2 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -520,6 +520,23 @@ per_bridge5: bus@2d800000 { #size-cells = <1>; ranges; + avd_sim: syscon@2da50000 { + compatible = "nxp,imx8ulp-avd-sim", "syscon"; + reg = <0x2da50000 0x38>; + clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + + avd_sim_rst: reset-controller { + compatible = "nxp,imx8ulp-avd-sim-reset"; + #reset-cells = <1>; + }; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>; -- 2.34.1