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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b671782d7bsm16621808a91.51.2024.05.17.03.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 03:25:20 -0700 (PDT) Date: Fri, 17 May 2024 19:25:18 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Siddharth Vadapalli Cc: bhelgaas@google.com, lpieralisi@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, vigneshr@ti.com, afd@ti.com, srk@ti.com Subject: Re: [PATCH v3] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC Message-ID: <20240517102518.GF202520@rocinante> References: <20240124122936.816142-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240124122936.816142-1-s-vadapalli@ti.com> Hello, > TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller. > The controller on J722S SoC is similar to the one present on TI's AM64 > SoC, with the difference being that the controller on AM64 SoC supports > up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed. > > Update the bindings with a new compatible for J722S SoC. > > Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3 Applied to dt-bindings, thank you! [1/1] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC https://git.kernel.org/pci/pci/c/01fec70206d4 Krzysztof