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AJvYcCUPsConh/4BUZC38SsA2fA9Rn5DVN9JGSI+q5jW5p3GLAbrb9a28oETPmRAewX1KyqzGOd/1BdASvJm8DVYGHLb432UcGhZqU1AkMAHmjCzYb6q2OWE/y328u5a1kmobn6QSvoc56Eajg== X-Gm-Message-State: AOJu0YzxCG2QmWRYnTE+V1B5gvmjzhPYCRPhBN3aECUXBx8Nsj+i2HqO GFcDI6gAP5W7KtyfC8kcAQjds76yTpos6ZFS3m386lT+sCmLUe6j X-Received: by 2002:a17:902:b414:b0:1e8:5cf9:37fc with SMTP id d9443c01a7336-1ef43e23f6bmr330376125ad.35.1716141572825; Sun, 19 May 2024 10:59:32 -0700 (PDT) Received: from localhost.localdomain ([223.178.84.79]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-1f2fc5a015esm9424325ad.14.2024.05.19.10.59.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 May 2024 10:59:32 -0700 (PDT) From: Kanak Shilledar X-Google-Original-From: Kanak Shilledar To: Cc: Kanak Shilledar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc: Date: Sun, 19 May 2024 23:29:04 +0530 Message-Id: <20240519175906.138410-1-kanakshilledar111@protonmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series of patches converts the RISC-V CPU interrupt controller to the newer dt-schema binding. Patch 1: This patch is currently at v3 as it has been previously rolled out. Contains the bindings for the interrupt controller. Patch 2: Contains the reference to the above interrupt controller. Thus, making all the RISC-V interrupt controller bindings in a centralized place. These patches are interdependent. Kanak Shilledar (2): dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema dt-bindings: riscv: cpus: add ref to interrupt-controller .../interrupt-controller/riscv,cpu-intc.txt | 52 ------------- .../interrupt-controller/riscv,cpu-intc.yaml | 73 +++++++++++++++++++ .../devicetree/bindings/riscv/cpus.yaml | 22 +----- 3 files changed, 74 insertions(+), 73 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23 prerequisite-patch-id: 158157d32a32e765834a0cb4fc6335f9009d9962 prerequisite-patch-id: 4007c7386e66f93b67a2631dddca08cadcee708b -- 2.34.1