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From: Sean Anderson To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-pci@vger.kernel.org Cc: Michal Simek , Thippeswamy Havalige , linux-arm-kernel@lists.infradead.org, Bjorn Helgaas , linux-kernel@vger.kernel.org, Sean Anderson Subject: [PATCH v3 7/7] arm64: zynqmp: Add PCIe phys Date: Mon, 20 May 2024 10:54:02 -0400 Message-Id: <20240520145402.2526481-8-sean.anderson@linux.dev> In-Reply-To: <20240520145402.2526481-1-sean.anderson@linux.dev> References: <20240520145402.2526481-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Add PCIe phy bindings for the ZCU102. Signed-off-by: Sean Anderson Tested-by: thippeswamy.havalige@amd.com --- (no changes since v2) Changes in v2: - Remove phy-names arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index ad8f23a0ec67..d2175f3dd099 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -941,6 +941,7 @@ conf-pull-none { &pcie { status = "okay"; + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; }; &psgtr { -- 2.35.1.1320.gc452695387.dirty