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Message-ID: <69e840a9-e5f4-4ae5-ab89-ae7d9f6367f8@broadcom.com>
Date: Mon, 20 May 2024 11:03:37 -0700
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Subject: Re: [PATCH v2 4/4] arm64: dts: broadcom: Add support for BCM2712
To: Florian Fainelli <florian.fainelli@broadcom.com>,
 Andrea della Porta <andrea.porta@suse.com>, Rob Herring <robh@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Conor Dooley <conor+dt@kernel.org>, Ray Jui <rjui@broadcom.com>,
 Scott Branden <sbranden@broadcom.com>,
 Broadcom internal kernel review list
 <bcm-kernel-feedback-list@broadcom.com>, Ulf Hansson
 <ulf.hansson@linaro.org>, Adrian Hunter <adrian.hunter@intel.com>,
 Kamal Dasu <kamal.dasu@broadcom.com>, Al Cooper <alcooperx@gmail.com>,
 Eric Anholt <eric@anholt.net>, Stefan Wahren <wahrenst@gmx.net>,
 devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org,
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 linux-mmc@vger.kernel.org
References: <cover.1715332922.git.andrea.porta@suse.com>
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 <786bbf35-e9fe-445c-b6f9-21119e60fb34@broadcom.com>
 <ZkXFi6_2DkXRNgSL@apocalypse>
From: Florian Fainelli <florian.fainelli@broadcom.com>
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In-Reply-To: <ZkXFi6_2DkXRNgSL@apocalypse>
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On 5/16/24 01:36, Andrea della Porta wrote:
> On 09:14 Fri 10 May     , Florian Fainelli wrote:
>> On 5/10/24 07:35, Andrea della Porta wrote:
>>
>> This should be #size-cells = <2> to be future proof and support over 4GB of
>> DRAM, because the DDR controller and the memory map on that chip have been
>> designed with that requirement.
>>
>>> +
>>> +	interrupt-parent = <&gicv2>;
>>> +
>>> +	axi: axi {
>>> +		compatible = "simple-bus";
>>> +		#address-cells = <2>;
>>> +		#size-cells = <1>;
>>> +		ranges;
>>
>> The AXI peripheral window should be defined in the ranges property. The
>> aperture is from 0x10_0000_0000 to 0x10_3FFF_FFFF.
>>
>>  From that point on you can define all peripherals under the axi node to be
>> relative to that axi aperture, just like what you did for the legacy Pi
>> peripherals in the subsequent bus node.
> 
> This doesn't seem to match with what I have here:
> - some axi peripherals goes beyond 0x10_3FFF_FFFF (e.g. the interrupt
>    controller is @0x107fff9000)

The interrupt controller (GIC) is technically its own dedicated bus to 
the CPU, that's why it is typically added to the root node.

> - downstream dts have that ranges going from 0x10 0x00000000 0x11 0x00000000,
>    so to span all the peripheral (included e.g. the above int controller)
> - another comment in downstream dts says: // 10_00000000-1x_xxxxxxxx = up to
>    64GB system RAM

Yes, up to 64GB of DRAM is correct.

> 
> I'm a little confused here, of course we could also define multiple ranges
> but I don't really know what the boundaries are. Anyway, I would opt for the
> extended range (0x10 0x00000000 - 0x11 0x00000000) unless there is concern
> about it. Any thoughts?

A single range is fine with me, those sort of details should not matter.

> 
> Many thanks,
> Andrea
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Florian


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