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Peter Anvin" , "Peter Zijlstra (Intel)" , Uros Bizjak , Rick Edgecombe , Arnd Bergmann , Tony Luck , Mateusz Guzik , Thomas Renninger , Andi Kleen , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Hans de Goede Subject: [PATCH v6 25/49] platform/x86/intel/pmc: Switch to new Intel CPU model defines Date: Mon, 20 May 2024 15:45:56 -0700 Message-ID: <20240520224620.9480-26-tony.luck@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240520224620.9480-1-tony.luck@intel.com> References: <20240520224620.9480-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Hans de Goede --- drivers/platform/x86/intel/pmc/core.c | 46 +++++++++++++-------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index 2ad2f8753e5d..65eb09c7af6a 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -1293,29 +1293,29 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) } static const struct x86_cpu_id intel_pmc_core_ids[] = { - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, spt_core_init), - X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, spt_core_init), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, spt_core_init), - X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, spt_core_init), - X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, cnp_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, icl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, icl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, cnp_core_init), - X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, cnp_core_init), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, tgl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, icl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, tgl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, adl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, tgl_l_core_init), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, adl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, adl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, mtl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(ARROWLAKE, arl_core_init), - X86_MATCH_INTEL_FAM6_MODEL(LUNARLAKE_M, lnl_core_init), + X86_MATCH_VFM(INTEL_SKYLAKE_L, spt_core_init), + X86_MATCH_VFM(INTEL_SKYLAKE, spt_core_init), + X86_MATCH_VFM(INTEL_KABYLAKE_L, spt_core_init), + X86_MATCH_VFM(INTEL_KABYLAKE, spt_core_init), + X86_MATCH_VFM(INTEL_CANNONLAKE_L, cnp_core_init), + X86_MATCH_VFM(INTEL_ICELAKE_L, icl_core_init), + X86_MATCH_VFM(INTEL_ICELAKE_NNPI, icl_core_init), + X86_MATCH_VFM(INTEL_COMETLAKE, cnp_core_init), + X86_MATCH_VFM(INTEL_COMETLAKE_L, cnp_core_init), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, tgl_l_core_init), + X86_MATCH_VFM(INTEL_TIGERLAKE, tgl_core_init), + X86_MATCH_VFM(INTEL_ATOM_TREMONT, tgl_l_core_init), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, icl_core_init), + X86_MATCH_VFM(INTEL_ROCKETLAKE, tgl_core_init), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, tgl_l_core_init), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, tgl_l_core_init), + X86_MATCH_VFM(INTEL_ALDERLAKE, adl_core_init), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, tgl_l_core_init), + X86_MATCH_VFM(INTEL_RAPTORLAKE, adl_core_init), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, adl_core_init), + X86_MATCH_VFM(INTEL_METEORLAKE_L, mtl_core_init), + X86_MATCH_VFM(INTEL_ARROWLAKE, arl_core_init), + X86_MATCH_VFM(INTEL_LUNARLAKE_M, lnl_core_init), {} }; -- 2.45.0