Received-SPF: pass (google.com: domain of linux-kernel+bounces-184524-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
Precedence: bulk
MIME-Version: 1.0
References: <1715939146-13031-1-git-send-email-shengjiu.wang@nxp.com>
 <1715939146-13031-2-git-send-email-shengjiu.wang@nxp.com> <4727a091-bc64-46ea-8652-db6797dd93d2@linaro.org>
In-Reply-To: <4727a091-bc64-46ea-8652-db6797dd93d2@linaro.org>
From: Shengjiu Wang <shengjiu.wang@gmail.com>
Date: Tue, 21 May 2024 14:32:32 +0800
Message-ID: <CAA+D8APgcZo4fhmzft83ZFeG2bfF19Ew5Fi4o5Gqh3Ej=OPCuA@mail.gmail.com>
Subject: Re: [PATCH 1/2] ASoC: dt-bindings: fsl,mqs: Add i.MX95 platform support
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Shengjiu Wang <shengjiu.wang@nxp.com>, lgirdwood@gmail.com, broonie@kernel.org, 
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, 
	linux-sound@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org, Xiubo.Lee@gmail.com, festevam@gmail.com, 
	nicoleotsuka@gmail.com, perex@perex.cz, tiwai@suse.com, 
	alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Mon, May 20, 2024 at 6:47=E2=80=AFPM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 17/05/2024 11:45, Shengjiu Wang wrote:
> > In order to support the MQS module on i.MX95, a new property
> > "fsl,mqs-ctrl" needs to be added, as there are two MQS instances
> > on the i.MX95 platform, the definition of bit positions in the
> > control register is different. This new property is to distinguish
> > these two instances.
> >
> > Without this property, the difference of platforms except the
> > i.MX95 was handled by the driver itself. But this new property can
> > also be used for previous platforms.
> >
> > The MQS only has one control register, the register may be
> > in General Purpose Register memory space, or MQS its own
> > memory space, or controlled by System Manager.
> > The bit position in the register may be different for each
> > platform, there are four parts (bits for module enablement,
> > bits for reset, bits for oversampling ratio, bits for divider ratio).
> > This new property includes all these things.
>
> ...
>
> >
> >    clocks:
> >      minItems: 1
> > @@ -45,6 +46,22 @@ properties:
> >    resets:
> >      maxItems: 1
> >
> > +  fsl,mqs-ctrl:
> > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > +    minItems: 6
> > +    maxItems: 6
> > +    description: |
> > +      Contains the control register information, defined as,
> > +      Cell #1: register type
> > +               0 - the register in owned register map
> > +               1 - the register in general purpose register map
> > +               2 - the register in control of system manager
> > +      Cell #2: offset of the control register from the syscon
> > +      Cell #3: shift bits for module enable bit
> > +      Cell #4: shift bits for reset bit
> > +      Cell #5: shift bits for oversampling ratio bit
> > +      Cell #6: shift bits for divider ratio control bit
>
> Thanks for detailed explanation in commit msg, but no, please do not
> describe layout of registers in DTS. For the syscon phandles, you can
> pass an argument (although not 6 arguments...). Usually this is enough.
> For some cases, like you have differences in capabilities of this device
> or its programming model, maybe you need different compatible.
>
> If these are different capabilities, sometimes new properties are
> applicable (describing hardware, not register bits...).
>
The main difference between the two instances on i.MX95 is the register
difference. looks like I need to use two compatible strings:
      - fsl,imx95-aonmix-mqs
      - fsl,imx95-netcmix-mqs
to distinguish them.

best regards
Shengjiu Wang

> Best regards,
> Krzysztof
>